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1. 发明授权

US07382662B2 Twin insulator charge storage device operation and its fabrication method 有权
标题翻译：双绝缘子电荷存储装置的操作及其制作方法
公开(公告)号：US07382662B2
公开(公告)日：2008-06-03
申请号：US11409247
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C11/34 , H01L23/58
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
摘要翻译：本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。控制栅极和字栅之间的垂直绝缘体不包括氮化物层。这样可以防止电子捕获的问题。可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

2. 发明授权

US07359250B2 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US07359250B2
公开(公告)日：2008-04-15
申请号：US11409333
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

3. 发明申请

US20070114597A1 Twin insulator charge storage device operation and its fabrication method 有权
标题翻译：双绝缘子电荷存储装置的操作及其制作方法
公开(公告)号：US20070114597A1
公开(公告)日：2007-05-24
申请号：US11652888
申请日：2007-01-12
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： H01L29/792
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/14 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/792
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
摘要翻译：本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。控制栅极和字栅之间的垂直绝缘体不包括氮化物层。这样可以防止电子捕获的问题。可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

4. 发明授权

US07170132B2 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US07170132B2
公开(公告)日：2007-01-30
申请号：US11059081
申请日：2005-02-16
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

5. 发明申请

US20060198200A1 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US20060198200A1
公开(公告)日：2006-09-07
申请号：US11409333
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

6. 发明授权

US07006378B1 Array architecture and operation methods for a nonvolatile memory 有权
标题翻译：非易失性存储器的阵列架构和操作方法
公开(公告)号：US07006378B1
公开(公告)日：2006-02-28
申请号：US10742987
申请日：2003-12-22
申请人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
发明人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.
摘要翻译：实现非易失性存储器件。该装置包括一串连接到源极的MONOS电池。每个MONOS单元包括覆盖衬底中的沟道区的字线门。第一和第二控制栅极，每个覆盖衬底中的沟道区域。字线栅极沟道区域横向在第一和第二控制栅极沟道区域之间。 ONO层在控制栅极和衬底之间垂直。 ONO层的氮化物层形成每个控制栅极的电荷存储位置。在衬底中形成源极和漏极的第一和第二掺杂区域。字线栅极沟道区和控制栅沟道区在第一掺杂区和第二掺杂区之间。第一和第二晶体管将最上面的MONOS单元连接到第一位线，将最底部的MONOS单元连接到第二位线。

7. 发明授权

US06838344B2 Simplified twin monos fabrication method with three extra masks to standard CMOS 有权
标题翻译：简单的双胞胎制造方法，具有三个额外的掩码到标准CMOS
公开(公告)号：US06838344B2
公开(公告)日：2005-01-04
申请号：US10853453
申请日：2004-05-25
申请人： Kimihiro Satoh , Tomoya Saito , Seiki Ogura
发明人： Kimihiro Satoh , Tomoya Saito , Seiki Ogura
IPC分类号： H01L21/8246 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.
摘要翻译：本发明提出简化双MONOS存储器阵列的制造。通过仅添加三个附加掩模级别，本发明的双MONOS存储器阵列可以嵌入到标准CMOS电路中。常规浮动栅极器件需要十个或更多个额外的掩模。在本发明中，独特的双MONOS工艺步骤可以插入到标准CMOS工艺流程中，无需任何参数修改。本发明还通过减小侧壁控制栅极和下面的氮化物存储区域的宽度来实现增加的耐久性。

8. 发明授权

US06670240B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06670240B2
公开(公告)日：2003-12-30
申请号：US10218210
申请日：2002-08-13
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L21336
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

9. 发明申请

US20060203562A1 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US20060203562A1
公开(公告)日：2006-09-14
申请号：US11409247
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

10. 发明授权

US07046556B2 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US07046556B2
公开(公告)日：2006-05-16
申请号：US11059080
申请日：2005-02-16
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

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