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1. 发明授权

US06628555B2 Semiconductor circuit having a detection circuit for controlling a power boosting circuit 有权
标题翻译：具有用于控制功率提升电路的检测电路的半导体电路
公开(公告)号：US06628555B2
公开(公告)日：2003-09-30
申请号：US10218307
申请日：2002-08-15
申请人： Masataka Kondo , Kiyoto Oota , Tomonori Fujimoto , Yoshihiko Sumimoto
发明人： Masataka Kondo , Kiyoto Oota , Tomonori Fujimoto , Yoshihiko Sumimoto
IPC分类号： G11C2900
CPC分类号： G11C11/4074 , G11C8/08
摘要： A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.
摘要翻译：包括在用于有效地稳定升压电位的半导体集成电路中的升压电路，包括多个升压电路和用于分配升压电路的操作的定时控制电路。存储器的每个操作周期的升压操作数量增加，以便抑制增强的源极电位的降低，这是由消耗引起的。此外，可以在与消耗升高的电位电位相同的时间段内进行升压操作，从而实现有效的升压操作。

2. 发明授权

US06459643B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06459643B2
公开(公告)日：2002-10-01
申请号：US09794771
申请日：2001-02-28
申请人： Masataka Kondo , Kiyoto Oota , Tomonori Fujimoto , Yoshihiko Sumimoto
发明人： Masataka Kondo , Kiyoto Oota , Tomonori Fujimoto , Yoshihiko Sumimoto
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C8/08
摘要： A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.
摘要翻译：包括在用于有效地稳定升压电位的半导体集成电路中的升压电路，包括多个升压电路和用于分配升压电路的操作的定时控制电路。存储器的每个操作周期的升压操作数量增加，以便抑制增强的源极电位的降低，这是由消耗引起的。此外，可以在与消耗升高的电位电位相同的时间段内执行升压操作，从而实现有效的升压操作。

3. 发明授权

US6122214A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US6122214A
公开(公告)日：2000-09-19
申请号：US273474
申请日：1999-03-22
申请人： Tomonori Fujimoto , Kiyoto Oota
发明人： Tomonori Fujimoto , Kiyoto Oota
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： In addition to a pulse train of a refresh request (RRQ) signal requesting for refresh per memory row, a self-refresh mode (SRMOD) signal is applied to a refresh control circuit. As soon as the SRMOD signal makes a transition from LOW to HIGH, an oscillation circuit starts generating a clock pulse train. In response to this clock pulse train, a set pulse is generated. A flip-flop circuit is set by the set pulse and a leading edge of a periodic refresh request (PRRQ) signal pulse is generated. Every time the PRRQ signal becomes HIGH, a reset pulse is generated, the flip-flop circuit is reset by the reset pulse, and a trailing edge of the PRRQ signal pulse is generated. Such arrangement provides a memory having a novel refresh input specification capable of reducing a burden of logic circuits for controlling access of the memory.
摘要翻译：除了刷新请求（RRQ）信号的脉冲串之外，还请求刷新控制电路的自刷新模式（SRMOD）信号。一旦SRMOD信号从低电平变为高电平，振荡电路开始产生时钟脉冲串。响应该时钟脉冲串，产生设定脉冲。触发器电路由设置脉冲设置，并且产生周期性刷新请求（PRRQ）信号脉冲的前沿。每当PRRQ信号变为高电平时，产生复位脉冲，触发电路被复位脉冲复位，产生PRRQ信号脉冲的后沿。这种布置提供具有新颖的刷新输入规范的存储器，其能够减少用于控制存储器访问的逻辑电路的负担。

4. 发明授权

US06349072B1 Random access memory device 失效
标题翻译：随机存取存储器件
公开(公告)号：US06349072B1
公开(公告)日：2002-02-19
申请号：US09705541
申请日：2000-11-03
申请人： Kenichi Origasa , Kiyoto Oota , Tomonori Fujimoto
发明人： Kenichi Origasa , Kiyoto Oota , Tomonori Fujimoto
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/409 , G11C2207/2281 , G11C2207/229
摘要： To realize a semiconductor memory which can be operated at a low frequency without reducing a data transfer rate, the semiconductor memory according to the invention is configured so that a series of operation can be finished in two clock cycles of row address strobe operation and column address strobe operation for operating DRAM. Timing for turning a sense amplifier activation signal SE at a high level after delay time determined by a first delay element since a leading edge of a clock pulse CLK that turns a row address strobe pulse (/RAS) at a low level and activating a sense amplifier sequence is generated. Also, timing for starting read operation and write operation since a leading edge of the clock pulse CLK at which a column address strobe pulse (/CAS) is turned at a low level, turning the sense amplifier activation signal SE at a low level, turning a bit line precharge signal EQPR at a high level and starting precharge operation when the termination of reading and writing is detected is acquired.
摘要翻译：为了实现能够以低频率操作而不降低数据传输速率的半导体存储器，根据本发明的半导体存储器被配置为使得可以在行地址选通操作和列地址的两个时钟周期中完成一系列操作频闪操作用于操作DRAM。用于在由第一延迟元件确定的延迟时间之后将读出放大器激活信号SE转换为高电平的时序，因为将行地址选通脉冲（/ RAS）变为低电平并激活感测的时钟脉冲CLK的前沿产生放大器序列。此外，从列位地址选通脉冲（/ CAS）转为低电平的时钟脉冲CLK的前沿开始读操作和写操作的定时，将读出放大器激活信号SE转为低电平，转动获取高电平的位线预充电信号EQPR和检测到读取和写入结束时的开始预充电操作。

5. 发明授权

US06864693B2 Semiconductor integrated circuit with negative voltage generation circuit, test method for the same, and recording device and communication equipment having the same 有权
标题翻译：具有负电压发生电路的半导体集成电路，与其相同的测试方法，以及具有该电路的记录装置和通信设备
公开(公告)号：US06864693B2
公开(公告)日：2005-03-08
申请号：US09852839
申请日：2001-05-10
申请人： Masataka Kondo , Kiyoto Ohta , Tomonori Fujimoto
发明人： Masataka Kondo , Kiyoto Ohta , Tomonori Fujimoto
IPC分类号： G01R31/28 , G11C11/401 , G11C11/408 , G11C29/02 , H01L21/822 , H01L27/04 , G01R27/08 , H01L21/31
CPC分类号： G01R31/2884
摘要： A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced. A voltage detection part 1-B included in the negative voltage generation circuit is provided with a constant voltage generation circuit 1-B1, a measuring voltage generation circuit 1-B3, which receives a constant voltage STDVOUT sent from the constant voltage generation circuit via a voltage supplying circuit 1-B2 and a negative voltage VBB sent from a negative voltage generation part and converts it into a measuring voltage REFV0 by resistors R1′, R2′, a first comparator AMP12, which compares the measuring voltage sent from the measuring voltage generation circuit with ground voltage and outputs the result of comparison, and an output buffer circuit 1-B4′, which amplifies the compared output from the first comparator and outputs it to the negative voltage generation part.
摘要翻译：提供了一种半导体集成电路，其中容易地实现了能够独立于电源电压或环境条件和处理条件等的波动来提供具有稳定的负电压的存储单元晶体管衬底的负电压产生电路，并且可以充分地确保存储器的数据保持时间，并且降低功耗。包括在负电压产生电路中的电压检测部分1-B设置有恒压产生电路1-B1，测量电压产生电路1-B3，其接收从恒压产生电路经由电压供给电路1-B2和从负电压产生部发送的负电压VBB，并将其通过电阻器R1'，R2'转换为测量电压REFV0，第一比较器AMP12将从测量电压产生电路，并输出比较结果;以及输出缓冲电路1-B4'，其放大来自第一比较器的比较输出并将其输出到负电压产生部分。

6. 发明授权

US07038967B2 Semiconductor apparatus capable of performing refresh control 有权
标题翻译：能够进行刷新控制的半导体装置
公开(公告)号：US07038967B2
公开(公告)日：2006-05-02
申请号：US10864814
申请日：2004-06-10
申请人： Toshitaka Uchikoba , Tomonori Fujimoto , Kiyoto Ohta
发明人： Toshitaka Uchikoba , Tomonori Fujimoto , Kiyoto Ohta
IPC分类号： G11C7/00 , G11C7/04
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40626
摘要： A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.
摘要翻译：根据本发明的半导体装置包括电流源，其根据温度的升高增加电流体积，并且由电流源的电流驱动的振荡电路，并输出用于刷新控制的时钟。半导体装置优选地还包括与振荡电路的输出时钟或其分频时钟同步地执行刷新的存储器件。半导体装置优选地还包括使用电流源产生恒定电压的恒定电压源，使用电流源的电流的振荡电路和使用由恒定电压源产生的恒定电压作为参考电压的存储器电源电路，并且与振荡电路的输出时钟或其分频时钟同步地进行刷新。

7. 发明授权

US06785187B2 Semiconductor device having integrated memory and logic 失效
标题翻译：具有集成存储器和逻辑的半导体器件
公开(公告)号：US06785187B2
公开(公告)日：2004-08-31
申请号：US10325932
申请日：2002-12-23
申请人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
发明人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
IPC分类号： G11C800
CPC分类号： G11C11/4082 , G11C8/06 , G11C29/48
摘要： In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.
摘要翻译：在常规DRAM中，行地址和列地址被DFF锁存，地址的解码在时钟上升之后的特定时间开始，并且在时钟上升直到解码完成之后需要很长时间，具有这样的问题不可能高速执行读/写。本发明采用使用扫描链连接诸如行地址锁存电路和列地址锁存电路的锁存电路的配置。这使得当时钟为“L”时，行地址和列地址的解码开始，使得可以在每个操作时钟周期的上升完成解码，缩短操作时钟周期并加快读/写速度。传统技术通过整个LSI的实际操作测试来对逻辑部分和存储器的行地址和列地址之间的连接进行测试，导致低电路故障检测率。本发明通过扫描测试进行该测试，使得可以自动创建具有高电路故障检测速率的测试图案。

8. 发明授权

US06654299B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06654299B2
公开(公告)日：2003-11-25
申请号：US09921564
申请日：2001-08-06
申请人： Hidefumi Otsuka , Tomonori Fujimoto
发明人： Hidefumi Otsuka , Tomonori Fujimoto
IPC分类号： G11C700
CPC分类号： G11C7/1012 , G11C7/1006 , G11C11/4093 , G11C11/4096 , G11C29/48
摘要： A semiconductor integrated circuit includes a plurality of semiconductor memory devices implemented as DRAMs and an output selector on the same chip. External terminals of the chip include: terminals for inputting an inverted row address strobe signal /RAS to the respective semiconductor memory devices individually; and common terminals for inputting PRAUT, SLF, /CAS, ADR, /WE, /OE, CLK and TMODE signals to all the memory devices. The output signals TDQ, SRAS, MOUT and BITST of the semiconductor memory devices are controlled by the output selector, passed through a common test bus and then output from a common external terminal.
摘要翻译：半导体集成电路包括实现为DRAM的多个半导体存储器件和在同一芯片上的输出选择器。芯片的外部端子包括：用于分别向各个半导体存储器件输入反相行地址选通信号/ RAS的端子; 以及用于向所有存储器件输入PRAUT，SLF，/ CAS，ADR，/ WE，/ OE，CLK和TMODE信号的公共端子。半导体存储器件的输出信号TDQ，SRAS，MOUT和BITST由输出选择器控制，通过公共测试总线，然后从公共外部端子输出。

9. 发明授权

US06532187B2 Semiconductor device having integrated memory and logic 有权
标题翻译：具有集成存储器和逻辑的半导体器件
公开(公告)号：US06532187B2
公开(公告)日：2003-03-11
申请号：US09867547
申请日：2001-05-31
申请人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
发明人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
IPC分类号： G11C800
CPC分类号： G11C11/4082 , G11C8/06 , G11C29/48
摘要： In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.
摘要翻译：在常规DRAM中，行地址和列地址被DFF锁存，地址的解码在时钟上升之后的特定时间开始，并且在时钟上升直到解码完成之后需要很长时间，具有这样的问题不可能高速执行读/写。本发明采用使用扫描链连接诸如行地址锁存电路和列地址锁存电路的锁存电路的配置。这使得当时钟为“L”时，行地址和列地址的解码开始，使得可以在每个操作时钟周期的上升完成解码，缩短操作时钟周期并加快读/写速度。传统技术通过整个LSI的实际操作测试来对逻辑部分和存储器的行地址和列地址之间的连接进行测试，导致低电路故障检测率。本发明通过扫描测试进行该测试，使得可以自动创建具有高电路故障检测速率的测试图案。

10. 发明授权

US07136312B2 Semiconductor device having read and write operations corresponding to read and write row control signals 有权
标题翻译：具有读和写操作对应于读和写行控制信号的半导体器件
公开(公告)号：US07136312B2
公开(公告)日：2006-11-14
申请号：US10918377
申请日：2004-08-16
申请人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
发明人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/12 , G11C11/4094 , G11C2207/002 , G11C2207/005
摘要： In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.
摘要翻译：在需要用于存储数据的刷新操作的半导体器件中，在页模式读取操作中通过位线对，读出放大器和数据线对来读取响应于行地址而选择的存储器单元的数据。此后，在将主放大器中保存的数据输出到外部的同时，连接晶体管被断开，从而将主放大器与存储单元断开，从而可以对存储单元进行预充电。此外，在页模式写入操作中，在将外部提供的输入数据写入主放大器中时，存储器单元可以被预充电。

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