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1. 发明授权

US06295243B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06295243B1
公开(公告)日：2001-09-25
申请号：US09449566
申请日：1999-11-29
申请人： Hidefumi Otsuka , Tomonori Fujimoto
发明人： Hidefumi Otsuka , Tomonori Fujimoto
IPC分类号： G11C700
CPC分类号： G11C7/1012 , G11C7/1006 , G11C11/4093 , G11C11/4096 , G11C29/48
摘要： A semiconductor integrated circuit includes a plurality of semiconductor memory devices implemented as DRAMs and an output selector on the same chip. External terminals of the chip include: terminals for inputting an inverted row address strobe signal /RAS to the respective semiconductor memory devices individually; and common terminals for inputting PRAUT, SLF, /CAS, ADR, /WE, /OE, CLK and TMODE signals to all the memory devices. The output signals TDQ, SRAS, MOUT and BITST of the semiconductor memory devices are controlled by the output selector, passed through a common test bus and then output from a common external terminal.
摘要翻译：半导体集成电路包括实现为DRAM的多个半导体存储器件和在同一芯片上的输出选择器。芯片的外部端子包括：用于分别向各个半导体存储器件输入反相行地址选通信号/ RAS的端子; 以及用于向所有存储器件输入PRAUT，SLF，/ CAS，ADR，/ WE，/ OE，CLK和TMODE信号的公共端子。半导体存储器件的输出信号TDQ，SRAS，MOUT和BITST由输出选择器控制，通过公共测试总线，然后从公共外部端子输出。

2. 发明授权

US06654299B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06654299B2
公开(公告)日：2003-11-25
申请号：US09921564
申请日：2001-08-06
申请人： Hidefumi Otsuka , Tomonori Fujimoto
发明人： Hidefumi Otsuka , Tomonori Fujimoto
IPC分类号： G11C700
CPC分类号： G11C7/1012 , G11C7/1006 , G11C11/4093 , G11C11/4096 , G11C29/48
摘要： A semiconductor integrated circuit includes a plurality of semiconductor memory devices implemented as DRAMs and an output selector on the same chip. External terminals of the chip include: terminals for inputting an inverted row address strobe signal /RAS to the respective semiconductor memory devices individually; and common terminals for inputting PRAUT, SLF, /CAS, ADR, /WE, /OE, CLK and TMODE signals to all the memory devices. The output signals TDQ, SRAS, MOUT and BITST of the semiconductor memory devices are controlled by the output selector, passed through a common test bus and then output from a common external terminal.
摘要翻译：半导体集成电路包括实现为DRAM的多个半导体存储器件和在同一芯片上的输出选择器。芯片的外部端子包括：用于分别向各个半导体存储器件输入反相行地址选通信号/ RAS的端子; 以及用于向所有存储器件输入PRAUT，SLF，/ CAS，ADR，/ WE，/ OE，CLK和TMODE信号的公共端子。半导体存储器件的输出信号TDQ，SRAS，MOUT和BITST由输出选择器控制，通过公共测试总线，然后从公共外部端子输出。

3. 发明授权

US5021810A Printing machine 失效
标题翻译：印刷机
公开(公告)号：US5021810A
公开(公告)日：1991-06-04
申请号：US542987
申请日：1990-06-25
申请人： Katsumi Muroi , Kenji Okuna , Hidefumi Otsuka , Kastubumi Ouchi , Tsutomu Iimura , Ryoji Kojima
发明人： Katsumi Muroi , Kenji Okuna , Hidefumi Otsuka , Kastubumi Ouchi , Tsutomu Iimura , Ryoji Kojima
IPC分类号： B41J2/385 , B41J2/43 , G03G15/05 , G03G15/34
CPC分类号： G03G15/348 , B41J2/43 , G03G2217/0033
摘要： A printing machine according to the present invention, comprises electrically conductive and magnetically inductive printing toner, an array of electrode-needles contacting with toner, each of the electrode-needles arranged apart from the adjacent electrode-needles in the array and individually energized in accordance with a desired printing pattern to electrify the toner communicating electrically with the energized electrode-needle, recording means including an electrically conductive portion and an insulating surface which extends on the electrically conductive portion and is arranged away from the array of electrode-needles to face thereto and to contact with the toner arranged between the electrode-needles and the insulating surface, the voltage applied to the electrically conductive portion being positive when the voltage applied to the energized electrode-needles is negative or the voltage applied to the electrically conductive portion being negative when the voltage applied to the energized electrode-needles is positive so that the toner electrified by the energized electrode-needle is attracted and attached to the insulating surface by the electrically conductive portion, the insulating surface moving in relation to the array of electrode-needles so that the toner is attached to an area of the insulating surface, magnetic means for attracting the magnetically inductive printing toner to form toner chains between the array of the electrode-needles and the insulating surface, and transferring means for transferring the toner from the insulating surface to a work piece, wherein longitudinally extending surfaces of the electrode-needles face to the insulating surface to electrify the printing toner arranged between the electrode-needles and the insulating surface.
摘要翻译：根据本发明的印刷机包括导电和磁感应印刷调色剂，与调色剂接触的电极针阵列，每个电极针布置在阵列中与相邻的电极针分开并且按照具有期望的印刷图案，以使与通电的电极针电气连通的调色剂通电，记录装置包括导电部分和在导电部分上延伸的绝缘表面，并且远离电极针阵列布置以面对它并且与布置在电极针和绝缘表面之间的调色剂接触，当施加到通电的电极针的电压为负时，施加到导电部分的电压为正，或者施加到导电部分的电压为负当施加电压时通电的电极针是正的，使得由通电的电极针带电的调色剂被导电部分吸引并附着到绝缘表面，绝缘表面相对于电极针阵列移动，使得调色剂附着在绝缘表面的区域上的磁性装置，用于吸引磁感应打印调色剂以在电极针阵列和绝缘表面之间形成调色剂链的磁性装置，以及用于将调色剂从绝缘表面转移到工件的转印装置其中电极针的纵向延伸的表面面向绝缘表面，以使设置在电极针和绝缘表面之间的印刷色粉带电。

4. 发明授权

US06556491B2 Semiconductor storage device and method of testing the same 有权
公开(公告)号：US06556491B2
公开(公告)日：2003-04-29
申请号：US09871932
申请日：2001-06-01
申请人： Hidefumi Otsuka , Yuji Yamasaki
发明人： Hidefumi Otsuka , Yuji Yamasaki
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/401 , G11C29/12 , H01L27/10897
摘要： A dynamic random access memory (DRAM) whose charge-holding characteristic regarding a leak of an electric charge through the bit line is tested in a short time is provided. The DRAM comprises a memory cell array including memory cells arranged at intersections of word lines and bit lines, plural sense amplifiers disposed at a pair of the bit lines, plural bit line pre-charge circuits for pre-charging and equalizing a potential in the pair of the bit lines, and a switching circuit for selecting an ordinary operation mode or a test mode. It further comprises a word line deactivator for deactivating all of word lines in the test mode, a sense amplifier deactivator for deactivating all of sense amplifiers in the test mode, and a bit line potential fixing circuit for fixing the bit lines to the same logic level of a high or a low level in the test mode.

5. 发明授权

US06175529B1 Semiconductor integrated circuit device and method for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06175529B1
公开(公告)日：2001-01-16
申请号：US09263839
申请日：1999-03-08
申请人： Hidefumi Otsuka , Shoji Sakamoto , Yuji Yamasaki
发明人： Hidefumi Otsuka , Shoji Sakamoto , Yuji Yamasaki
IPC分类号： G11C2900
CPC分类号： G11C29/30 , G11C29/14 , G11C29/36 , G11C29/40
摘要： For enabling the self-test of a memory with a small number of input and output pins, and the burn-in tests of a memory and a logic to be carried out simultaneously in a memory/logic circuit mixed system LSI, a test data, an address and a memory control signal required for the test of the memory are generated using the divided-frequency output signal of an address generator, i.e., frequency-divider of an external clock, and a mixer circuit for periodically inverting a pass/fail signal as the test result is provided. This enables the test of the memory with a total of 2 pins of input and output in all. Thus, it becomes possible to test the memory and the logic circuit simultaneously at the time of burn-in test thereof.
摘要翻译：为了实现具有少量输入和输出引脚的存储器的自检，以及在存储器/逻辑电路混合系统LSI中同时执行存储器和逻辑的老化测试，测试数据，使用地址发生器的分频输出信号（即，外部时钟的分频器）和用于周期性地反转通过/失败信号的混频器电路产生用于存储器测试所需的地址和存储器控制信号随着测试结果的提供。这使得能够对所有存储器进行总共2个输入和输出引脚的测试。因此，可以在其老化测试时同时测试存储器和逻辑电路。

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