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1. 发明授权

US06864693B2 Semiconductor integrated circuit with negative voltage generation circuit, test method for the same, and recording device and communication equipment having the same 有权
标题翻译：具有负电压发生电路的半导体集成电路，与其相同的测试方法，以及具有该电路的记录装置和通信设备
公开(公告)号：US06864693B2
公开(公告)日：2005-03-08
申请号：US09852839
申请日：2001-05-10
申请人： Masataka Kondo , Kiyoto Ohta , Tomonori Fujimoto
发明人： Masataka Kondo , Kiyoto Ohta , Tomonori Fujimoto
IPC分类号： G01R31/28 , G11C11/401 , G11C11/408 , G11C29/02 , H01L21/822 , H01L27/04 , G01R27/08 , H01L21/31
CPC分类号： G01R31/2884
摘要： A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced. A voltage detection part 1-B included in the negative voltage generation circuit is provided with a constant voltage generation circuit 1-B1, a measuring voltage generation circuit 1-B3, which receives a constant voltage STDVOUT sent from the constant voltage generation circuit via a voltage supplying circuit 1-B2 and a negative voltage VBB sent from a negative voltage generation part and converts it into a measuring voltage REFV0 by resistors R1′, R2′, a first comparator AMP12, which compares the measuring voltage sent from the measuring voltage generation circuit with ground voltage and outputs the result of comparison, and an output buffer circuit 1-B4′, which amplifies the compared output from the first comparator and outputs it to the negative voltage generation part.
摘要翻译：提供了一种半导体集成电路，其中容易地实现了能够独立于电源电压或环境条件和处理条件等的波动来提供具有稳定的负电压的存储单元晶体管衬底的负电压产生电路，并且可以充分地确保存储器的数据保持时间，并且降低功耗。包括在负电压产生电路中的电压检测部分1-B设置有恒压产生电路1-B1，测量电压产生电路1-B3，其接收从恒压产生电路经由电压供给电路1-B2和从负电压产生部发送的负电压VBB，并将其通过电阻器R1'，R2'转换为测量电压REFV0，第一比较器AMP12将从测量电压产生电路，并输出比较结果;以及输出缓冲电路1-B4'，其放大来自第一比较器的比较输出并将其输出到负电压产生部分。

2. 发明授权

US06532187B2 Semiconductor device having integrated memory and logic 有权
标题翻译：具有集成存储器和逻辑的半导体器件
公开(公告)号：US06532187B2
公开(公告)日：2003-03-11
申请号：US09867547
申请日：2001-05-31
申请人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
发明人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
IPC分类号： G11C800
CPC分类号： G11C11/4082 , G11C8/06 , G11C29/48
摘要： In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.
摘要翻译：在常规DRAM中，行地址和列地址被DFF锁存，地址的解码在时钟上升之后的特定时间开始，并且在时钟上升直到解码完成之后需要很长时间，具有这样的问题不可能高速执行读/写。本发明采用使用扫描链连接诸如行地址锁存电路和列地址锁存电路的锁存电路的配置。这使得当时钟为“L”时，行地址和列地址的解码开始，使得可以在每个操作时钟周期的上升完成解码，缩短操作时钟周期并加快读/写速度。传统技术通过整个LSI的实际操作测试来对逻辑部分和存储器的行地址和列地址之间的连接进行测试，导致低电路故障检测率。本发明通过扫描测试进行该测试，使得可以自动创建具有高电路故障检测速率的测试图案。

3. 发明授权

US07136312B2 Semiconductor device having read and write operations corresponding to read and write row control signals 有权
标题翻译：具有读和写操作对应于读和写行控制信号的半导体器件
公开(公告)号：US07136312B2
公开(公告)日：2006-11-14
申请号：US10918377
申请日：2004-08-16
申请人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
发明人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/12 , G11C11/4094 , G11C2207/002 , G11C2207/005
摘要： In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.
摘要翻译：在需要用于存储数据的刷新操作的半导体器件中，在页模式读取操作中通过位线对，读出放大器和数据线对来读取响应于行地址而选择的存储器单元的数据。此后，在将主放大器中保存的数据输出到外部的同时，连接晶体管被断开，从而将主放大器与存储单元断开，从而可以对存储单元进行预充电。此外，在页模式写入操作中，在将外部提供的输入数据写入主放大器中时，存储器单元可以被预充电。

4. 发明申请

US20050128786A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050128786A1
公开(公告)日：2005-06-16
申请号：US11006588
申请日：2004-12-08
申请人： Hidefumi Ohtsuka , Kiyoto Ohta , Tomonori Fujimoto
发明人： Hidefumi Ohtsuka , Kiyoto Ohta , Tomonori Fujimoto
IPC分类号： G11C11/407 , G11C8/08 , G11C11/4074 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4074
摘要： In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.
摘要翻译：为了降低电源电路的电路规模和半导体衬底上的电源电路所占据的面积，向存储电路的各个部分提供电源电压的电源电路包括字驱动器电源（第一电源电路），感测放大器电源（第二电源电路），位线预充电电源，单元板电源，衬底偏置电源以及字线偏置电源。字驱动器电源为字驱动器提供通过直接增加外部电源电压而产生的电压，而另一个电源（例如，读出放大器电源）为读出放大器等提供电压，通过减少外部电源电压。

5. 发明授权

US06621753B2 Semiconductor device 有权
公开(公告)号：US06621753B2
公开(公告)日：2003-09-16
申请号：US10323746
申请日：2002-12-20
申请人： Tomonori Fujimoto , Kiyoto Ohta , Yuji Yamasaki
发明人： Tomonori Fujimoto , Kiyoto Ohta , Yuji Yamasaki
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.

6. 发明授权

US07158424B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07158424B2
公开(公告)日：2007-01-02
申请号：US11006588
申请日：2004-12-08
申请人： Hidefumi Ohtsuka , Kiyoto Ohta , Tomonori Fujimoto
发明人： Hidefumi Ohtsuka , Kiyoto Ohta , Tomonori Fujimoto
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/4074
摘要： In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.
摘要翻译：为了降低电源电路的电路规模和半导体衬底上的电源电路所占据的面积，向存储电路的各个部分提供电源电压的电源电路包括字驱动器电源（第一电源电路），感测放大器电源（第二电源电路），位线预充电电源，单元板电源，衬底偏置电源以及字线偏置电源。字驱动器电源为字驱动器提供通过直接增加外部电源电压而产生的电压，而另一个电源（例如，读出放大器电源）为读出放大器等提供电压，通过减少外部电源电压。

7. 发明授权

US06999368B2 Semiconductor memory device and semiconductor integrated circuit device 失效
标题翻译：半导体存储器件和半导体集成电路器件
公开(公告)号：US06999368B2
公开(公告)日：2006-02-14
申请号：US10847392
申请日：2004-05-18
申请人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
发明人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4061
摘要： A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.
摘要翻译：半导体存储器件的行控制电路包括作为用于产生内部时钟的时钟振荡器的振荡器，作为用于与内部时钟同步产生刷新请求信号RFRQ的刷新请求信号RFRQ生成电路的D触发器，以及延迟电路 NAND门，AND门，D触发器，延迟电路，AND门和OR门作为刷新电路。通过使用刷新请求信号RFRQ和有效信号ACT，与外部刷新命令分开地在DRAM内部进行内部刷新。

8. 发明申请

US20050057987A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050057987A1
公开(公告)日：2005-03-17
申请号：US10918377
申请日：2004-08-16
申请人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
发明人： Tomonori Fujimoto , Kiyoto Ohta , Hirohito Kikukawa
IPC分类号： G11C11/409 , G11C7/12 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/406 , G11C7/12 , G11C11/4094 , G11C2207/002 , G11C2207/005
摘要： According to the invention, in a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.
摘要翻译：根据本发明，在需要用于存储数据的刷新操作的半导体器件中，响应于行地址选择的存储器单元的数据通过页模式中的位线对，读出放大器和数据线对读取到主放大器读操作。此后，在将主放大器中保存的数据输出到外部的同时，连接晶体管被断开，从而将主放大器与存储单元断开，从而可以对存储单元进行预充电。此外，在页模式写入操作中，在将外部提供的输入数据写入主放大器中时，存储器单元可以被预充电。

9. 发明申请

US20050052923A1 Semiconductor apparatus capable of performing refresh control 有权
标题翻译：能够进行刷新控制的半导体装置
公开(公告)号：US20050052923A1
公开(公告)日：2005-03-10
申请号：US10864814
申请日：2004-06-10
申请人： Toshitaka Uchikoba , Tomonori Fujimoto , Kiyoto Ohta
发明人： Toshitaka Uchikoba , Tomonori Fujimoto , Kiyoto Ohta
IPC分类号： H03K3/03 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40626
摘要： A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.
摘要翻译：根据本发明的半导体装置包括电流源，其根据温度的升高增加电流体积，并且由电流源的电流驱动的振荡电路，并输出用于刷新控制的时钟。半导体装置优选地还包括与振荡电路的输出时钟或其分频时钟同步地执行刷新的存储器件。半导体装置优选地还包括使用电流源产生恒定电压的恒定电压源，使用电流源的电流的振荡电路和使用由恒定电压源产生的恒定电压作为参考电压的存储器电源电路，并且与振荡电路的输出时钟或其分频时钟同步地进行刷新。

10. 发明授权

US06507529B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06507529B2
公开(公告)日：2003-01-14
申请号：US10003430
申请日：2001-12-06
申请人： Tomonori Fujimoto , Kiyoto Ohta , Yuji Yamasaki
发明人： Tomonori Fujimoto , Kiyoto Ohta , Yuji Yamasaki
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.
摘要翻译：一种能够刷新多个存储单元的半导体器件。在操作中，当请求数据读取操作时，a /行选择控制信号被输入到行选择控制电路的设置/复位电路，由此输出H电平隐藏刷新控制信号，并且内部行选择控制信号转换到 H级。结果，选择预期的字线，并且启动刷新操作。然后，在感测操作完成之后，通过延迟电路将感测放大器激活完成信号SEND输入到设置/复位电路，并且内部行选择控制信号转换到L电平。在通过三个延迟电路之后，读出放大器激活完成信号SEND被输入到另一个设置/复位电路，并且RW行选择控制信号转换到H电平，从而进行数据读取操作。

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