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1. 发明申请

US20070134922A1 Plasma etching method 失效
标题翻译：等离子蚀刻法
公开(公告)号：US20070134922A1
公开(公告)日：2007-06-14
申请号：US11354919
申请日：2006-02-16
申请人： Masahito Mori , Toshiaki Nishida , Naoshi Itabashi , Motohiko Yoshigai , Hideyuki Kazumi , Kazutami Tago
发明人： Masahito Mori , Toshiaki Nishida , Naoshi Itabashi , Motohiko Yoshigai , Hideyuki Kazumi , Kazutami Tago
IPC分类号： H01L21/302
CPC分类号： H01L21/32136 , H01L21/28123 , H01L21/31138 , H01L21/32137 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L22/26 , H01L29/66795
摘要： An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or “high-k” insulator is provided. To this end, place a workpiece on a lower electrode located within a vacuum processing vessel. The workpiece has a multilayer structure of an electrode material layer which contains therein a transition metal element and a dielectric material layer made of high-k insulator. Then, while introducing a processing gas into the vacuum processing vessel, high-frequency power is applied to inside of the vacuum processing vessel, thereby performing plasma conversion of the introduced processing gas so that the workpiece is etched at its surface. When etching the electrode material layer, an HCl gas is supplied as the processing gas.
摘要翻译：提供一种能够以高选择性对在由高介电常数或“高k”绝缘体制成的电介质材料层上形成的含过渡金属元素的电极材料层进行蚀刻的蚀刻技术。为此，将工件放置在位于真空处理容器内的下电极上。工件具有电极材料层的多层结构，其中包含过渡金属元件和由高k绝缘体制成的电介质材料层。然后，在将真空处理容器内的处理气体导入真空处理容器的内部的同时，向真空处理容器的内部施加高频电力，进行等离子体转换，使工件在其表面被蚀刻。当蚀刻电极材料层时，作为处理气体供给HCl气体。

2. 发明授权

US07442651B2 Plasma etching method 失效
标题翻译：等离子蚀刻法
公开(公告)号：US07442651B2
公开(公告)日：2008-10-28
申请号：US11354919
申请日：2006-02-16
申请人： Masahito Mori , Toshiaki Nishida , Naoshi Itabashi , Motohiko Yoshigai , Hideyuki Kazumi , Kazutami Tago
发明人： Masahito Mori , Toshiaki Nishida , Naoshi Itabashi , Motohiko Yoshigai , Hideyuki Kazumi , Kazutami Tago
IPC分类号： H91L21/302
CPC分类号： H01L21/32136 , H01L21/28123 , H01L21/31138 , H01L21/32137 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L22/26 , H01L29/66795
摘要： An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or “high-k” insulator is provided. To this end, place a workpiece on a lower electrode located within a vacuum processing vessel. The workpiece has a multilayer structure of an electrode material layer which contains therein a transition metal element and a dielectric material layer made of high-k insulator. Then, while introducing a processing gas into the vacuum processing vessel, high-frequency power is applied to inside of the vacuum processing vessel, thereby performing plasma conversion of the introduced processing gas so that the workpiece is etched at its surface. When etching the electrode material layer, an HCl gas is supplied as the processing gas.
摘要翻译：提供一种能够以高选择性对在由高介电常数或“高k”绝缘体制成的电介质材料层上形成的含过渡金属元素的电极材料层进行蚀刻的蚀刻技术。为此，将工件放置在位于真空处理容器内的下电极上。工件具有电极材料层的多层结构，其中包含过渡金属元件和由高k绝缘体制成的电介质材料层。然后，在将真空处理容器内的处理气体导入真空处理容器的内部的同时，向真空处理容器的内部施加高频电力，进行等离子体转换，使工件在其表面被蚀刻。当蚀刻电极材料层时，作为处理气体供给HCl气体。

3. 发明授权

US06309980B1 Semiconductor integrated circuit arrangement fabrication method 有权
标题翻译：半导体集成电路布置制造方法
公开(公告)号：US06309980B1
公开(公告)日：2001-10-30
申请号：US09564754
申请日：2000-05-04
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L2100
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用并选择性地获得期望的解离物种。

4. 发明授权

US09640366B2 Electron beam irradiation method and scanning electron microscope 有权
公开(公告)号：US09640366B2
公开(公告)日：2017-05-02
申请号：US13580288
申请日：2011-02-09
申请人： Toshiyuki Yokosuka , Minoru Yamazaki , Hideyuki Kazumi , Kazutami Tago
发明人： Toshiyuki Yokosuka , Minoru Yamazaki , Hideyuki Kazumi , Kazutami Tago
IPC分类号： H01J37/28 , H01J37/02 , H01J37/26
CPC分类号： H01J37/28 , H01J37/026 , H01J37/266 , H01J37/268 , H01J2237/0048 , H01J2237/24564 , H01J2237/2594
摘要： The present invention has for its object to provide a charged particle beam irradiation method and a charged particle beam apparatus which can suppress unevenness of electrification even when a plurality of different kinds of materials are contained in a pre-dosing area or degrees of density of patterns inside the pre-dosing area differs with positions.To accomplish the above object, a charged particle beam irradiation method and a charged particle beam apparatus are provided according to which the pre-dosing area is divided into a plurality of divisional areas and electrifications are deposited to the plural divisional areas by using a beam under different beam irradiation conditions. With the above construction, the electrifications can be deposited to the pre-dosing area on the basis of such an irradiation condition that the differences in electrification at individual positions inside the pre-dosing area can be suppressed and consequently, an influence an electric field has upon the charged particle beam and electrons given off from the sample can be suppressed.

5. 发明授权

US5962347A Semiconductor integrated circuit arrangement fabrication method 有权
公开(公告)号：US5962347A
公开(公告)日：1999-10-05
申请号：US188371
申请日：1998-11-10
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/70 , H01L21/768 , H01L21/77 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

6. 发明申请

US20130009057A1 Electron Beam Irradiation Method and Scanning Electron Microscope 有权
标题翻译：电子束照射方法和扫描电子显微镜
公开(公告)号：US20130009057A1
公开(公告)日：2013-01-10
申请号：US13580288
申请日：2011-02-09
申请人： Toshiyuki Yokosuka , Minoru Yamazaki , Hideyuki Kazumi , Kazutami Tago
发明人： Toshiyuki Yokosuka , Minoru Yamazaki , Hideyuki Kazumi , Kazutami Tago
IPC分类号： H01J37/29
CPC分类号： H01J37/28 , H01J37/026 , H01J37/266 , H01J37/268 , H01J2237/0048 , H01J2237/24564 , H01J2237/2594
摘要： The present invention has for its object to provide a charged particle beam irradiation method and a charged particle beam apparatus which can suppress unevenness of electrification even when a plurality of different kinds of materials are contained in a pre-dosing area or degrees of density of patterns inside the pre-dosing area differs with positions.To accomplish the above object, a charged particle beam irradiation method and a charged particle beam apparatus are provided according to which the pre-dosing area is divided into a plurality of divisional areas and electrifications are deposited to the plural divisional areas by using a beam under different beam irradiation conditions. With the above construction, the electrifications can be deposited to the pre-dosing area on the basis of such an irradiation condition that the differences in electrification at individual positions inside the pre-dosing area can be suppressed and consequently, an influence an electric field has upon the charged particle beam and electrons given off from the sample can be suppressed.
摘要翻译：本发明的目的是提供一种带电粒子束照射方法和带电粒子束装置，其即使在预给料区域中包含多种不同种类的材料或图案密度程度时也能抑制通电不均匀性预给药区域内的位置与位置不同。为了实现上述目的，提供一种带电粒子束照射方法和带电粒子束装置，根据该装置，预给料区域被分成多个分区，并且通过使用下面的束将电气沉积到多个分区域不同的束照射条件。通过上述结构，可以基于这样一种照射条件将电气沉积到预给料区域，即可以抑制预给料区域内各个位置的通电差异，从而影响电场可以抑制带电粒子束和从样品发出的电子。

7. 再颁专利

USRE39895E1 Semiconductor integrated circuit arrangement fabrication method 有权
标题翻译：半导体集成电路布置制造方法
公开(公告)号：USRE39895E1
公开(公告)日：2007-10-23
申请号：US10094157
申请日：2002-03-08
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/31116
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用并选择性地获得期望的解离物种。

8. 发明授权

US06074958A Semiconductor integrated circuit arrangement fabrication method 有权
标题翻译：半导体集成电路布置制造方法
公开(公告)号：US06074958A
公开(公告)日：2000-06-13
申请号：US339041
申请日：1999-06-23
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/70 , H01L21/768 , H01L21/77 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用并选择性地获得期望的解离物种。

9. 发明授权

US5874013A Semiconductor integrated circuit arrangement fabrication method 失效
标题翻译：半导体集成电路布置制造方法
公开(公告)号：US5874013A
公开(公告)日：1999-02-23
申请号：US857167
申请日：1997-05-15
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/70 , H01L21/768 , H01L21/77 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other, and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用，并且选择性地获得所需的解离物种。

10. 发明申请

US20090011592A1 METHOD OF MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路器件和半导体集成电路器件的制造方法
公开(公告)号：US20090011592A1
公开(公告)日：2009-01-08
申请号：US12194044
申请日：2008-08-19
申请人： Shouichi Uno , Atsushi Maekawa , Takashi Yunogami , Kazutami Tago , Kazuo Nojiri , Shuntaro Machida , Takafumi Tokunaga
发明人： Shouichi Uno , Atsushi Maekawa , Takashi Yunogami , Kazutami Tago , Kazuo Nojiri , Shuntaro Machida , Takafumi Tokunaga
IPC分类号： H01L21/768
CPC分类号： H01L21/02126 , H01L21/0217 , H01L21/022 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835
摘要： In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
摘要翻译：在制造具有嵌入式互连结构的半导体集成电路器件的方法中，通过将导体膜嵌入形成在构成层间电介质膜的有机绝缘膜中的凹槽（例如沟槽或孔）中并且包括有机硅氧烷作为通过在CF基气体/ N 2 / Ar气体中对有机绝缘膜进行等离子体干蚀刻来形成主要部件，凹槽，例如沟槽或孔，以抑制底部形成异常形状在有机绝缘膜上形成光致抗蚀剂膜之后，随后用光致抗蚀剂膜作为蚀刻掩模形成凹部。

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