专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07873871B2 Communication control system and communication control method 有权
标题翻译：通讯控制系统及通讯控制方法
公开(公告)号：US07873871B2
公开(公告)日：2011-01-18
申请号：US11768241
申请日：2007-06-26
申请人： Masakazu Ishikawa , Akira Bandou , Masahiro Shiraishi , Masamitsu Kobayashi , Yasuyuki Furuta , Akihiro Onozuka , Shin Kokura , Eiji Kobayashi , Satoru Funaki , Takashi Umehara , Naoya Mashiko , Yuusuke Seki , Tatsuyuki Ootani
发明人： Masakazu Ishikawa , Akira Bandou , Masahiro Shiraishi , Masamitsu Kobayashi , Yasuyuki Furuta , Akihiro Onozuka , Shin Kokura , Eiji Kobayashi , Satoru Funaki , Takashi Umehara , Naoya Mashiko , Yuusuke Seki , Tatsuyuki Ootani
IPC分类号： G06F11/00
CPC分类号： G05B23/0229 , G05B23/0262
摘要： A programmable electronic controller in which one central arithmetic processing unit and a plurality of input devices and output devices are connected by means of a parallel bus, the controller being basically configured to activate a self-diagnostic function and a diagnostic test of the input devices and the output devices with an instruction from a microprocessor of the central arithmetic processing unit; and to judge the result with the microprocessor of the central arithmetic processing unit, by using the microprocessor installed in the central arithmetic processing unit also as a processor for tests (diagnostic tests) of the self-diagnostic function of the input devices and output devices and conducting tests of the self-diagnostic function of the plurality of input devices and output devices with the central arithmetic processing unit.
摘要翻译：一种可编程电子控制器，其中一个中央算术处理单元和多个输入设备和输出设备通过并行总线连接，所述控制器基本上被配置为激活输入设备的自诊断功能和诊断测试，所述输出装置具有来自所述中央算术处理单元的微处理器的指令; 并且通过使用安装在中央算术处理单元中的微处理器作为输入设备和输出设备的自诊断功能的测试（诊断测试）的处理器来判断结果与中央算术处理单元的微处理器，以及利用中央算术处理单元对多个输入装置和输出装置进行自诊断功能的测试。

2. 发明授权

US07555627B2 Input-output control apparatus, input-output control method, process control apparatus and process control method 有权
标题翻译：输入输出控制装置，输入输出控制方法，过程控制装置和过程控制方法
公开(公告)号：US07555627B2
公开(公告)日：2009-06-30
申请号：US11477468
申请日：2006-06-30
申请人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
发明人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/122 , Y02P90/14
摘要： Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
摘要翻译：通过提供输入输出控制装置，通过提供输入输出控制装置来防止输入输出装置由于处理器使用的输入输出值，以便以具有较高安全性要求的模式进行算术运算第一存储区域，存储由处理器在具有相对较低安全性要求的模式下进行算术运算的输入输出值，并将其限制在第一存储区域中，并将复制从第一存储区域区域，复制到第二存储区域，或者根据关于安全性要求的模式从第二存储区域进行复制。

3. 发明授权

US5699541A Memory system using schottky diodes to reduce load capacitance 失效
标题翻译：使用肖特基二极管降低负载电容的存储系统
公开(公告)号：US5699541A
公开(公告)日：1997-12-16
申请号：US406147
申请日：1995-03-20
申请人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
发明人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
IPC分类号： G11C11/417 , G06F13/16 , G11C7/10 , G11C11/409 , G06F12/00 , G06F9/26 , G06F9/32 , G06F12/02
CPC分类号： G11C7/1051 , G11C7/1078
摘要： A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.
摘要翻译：公开了具有输入/输出电路的计算机存储器系统，该输入/输出电路能够将连接到存储器总线的半导体存储器的输出电路的负载电容与存储器总线分开。为了分离连接到存储器总线信号线的半导体存储器的负载电容，在半导体存储器和存储器总线之间布置肖特基二极管，并且提供电压控制电路以控制是否施加反向偏置电压到肖特基二极管。即使当半导体存储器的负载电容与总线分离时，即使大量的半导体存储器连接到存储器总线，信号传输的速度也不会降低。因此，可以构建高速，大容量的存储系统。

4. 发明申请

US20110302393A1 CONTROL SYSTEMS AND DATA PROCESSING METHOD 审中-公开
标题翻译：控制系统和数据处理方法
公开(公告)号：US20110302393A1
公开(公告)日：2011-12-08
申请号：US13153724
申请日：2011-06-06
申请人： Noritaka Matsumoto , Tsutomu Yamada , Akihiro Ohashi , Shin Kokura
发明人： Noritaka Matsumoto , Tsutomu Yamada , Akihiro Ohashi , Shin Kokura
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G05B19/052 , G05B2219/13028 , G05B2219/15114
摘要： When executing sequential processing such as a ladder logic, converting a program formed of an instruction set of another processor to a program executable by an own processor in software and then conducting processing lowers the real time property. In a control system, a storage unit stores a program for the own processor and a program for another processor. A processor reads data from the storage unit, executes processing described as a program, and gives an instruction to change over a method for acquiring data from the storage unit, to a conversion instruction unit according to data contents. A changeover unit is connected to the storage unit directly or via the conversion unit to change over the data acquiring method according to an instruction from the conversion instruction unit. The conversion unit converts data read from the storage unit to data executable by the processor, according to a conversion scheme.
摘要翻译：当执行诸如梯形逻辑的顺序处理时，将由另一处理器的指令集形成的程序转换成由软件可由自己的处理器执行的程序，然后执行处理降低实时属性。在控制系统中，存储单元存储用于自己的处理器的程序和用于另一个处理器的程序。处理器从存储单元读取数据，执行作为程序描述的处理，并且根据数据内容给出将从存储单元获取数据的方法改变为转换指令单元的指令。切换单元直接或经由转换单元连接到存储单元，以根据来自转换指令单元的指令改变数据获取方法。转换单元根据转换方案将从存储单元读取的数据转换为可由处理器执行的数据。

5. 发明申请

US20110113277A1 PROCESSING UNIT, PROCESS CONTROL SYSTEM AND CONTROL METHOD 有权
标题翻译：加工单元，过程控制系统和控制方法
公开(公告)号：US20110113277A1
公开(公告)日：2011-05-12
申请号：US12938557
申请日：2010-11-03
申请人： Noritaka Matsumoto , Tsutomu Yamada , Eiji Kobayashi , Akihiro Ohashi , Shin Kokura
发明人： Noritaka Matsumoto , Tsutomu Yamada , Eiji Kobayashi , Akihiro Ohashi , Shin Kokura
IPC分类号： G06F1/12
CPC分类号： G06F11/0766 , G06F11/0724 , G06F11/076
摘要： A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.
摘要翻译：处理单元通过由串行信号通信线路和同步信号通信线路组成的系统总线连接到另一个处理单元，以能够与其通信。当操作单元检测到处理单元中的异常状态时，操作单元将异常状态的检测通知提供给同步单元。同步单元通过同步信号通信线路将接收到的异常状态的检测通知发送给其他处理单元。转换单元通过重要信号线代替通用信号线从操作单元接收并行通信数据，并将接收到的并行信号转换为串行信号，以通过串行信号通信线路发送到另一个处理单元，从而在连接到当系统总线被配置为实现串行通信时，确保系统总线。

6. 发明申请

US20110022936A1 SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD 失效
标题翻译：发送装置，接收装置，通信控制装置，通信系统和通信控制方法
公开(公告)号：US20110022936A1
公开(公告)日：2011-01-27
申请号：US12900988
申请日：2010-10-08
申请人： Akihiro ONOZUKA , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
发明人： Akihiro ONOZUKA , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L1/0046
摘要： A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.
摘要翻译：一种接收装置，包括：接收器，接收两个帧，每个帧分别包括与数据错误检测码相关的基本相同的数据，帧错误检测码和表示安全功能的安全标志信息; 连接到接收机的第一检测器，分别通过使用帧错误检测码来进行帧的错误检测; 连接到所述接收器的第二检测器，用于分别通过使用所述数据检错码执行所述数据的错误检测; 以及连接到第一和第二检测器的直接存储器访问控制器（DMAC），用于在帧中没有检测到错误的两帧中的安全功能的条件下输出包括在两个帧中的数据之一，并且数据错误检测。

7. 发明申请

US20090319756A1 Duplexed operation processor control system, and duplexed operation processor control method 有权
标题翻译：双工操作处理器控制系统，双工操作处理器控制方式
公开(公告)号：US20090319756A1
公开(公告)日：2009-12-24
申请号：US12457682
申请日：2009-06-18
申请人： Toshiki Shimizu , Akira Bando , Yusaku Otsuka , Yasuhiro Kiyofuji , Elji Kobayashi , Akihiro Onozuka , Satoru Funaki , Masakazu Ishikawa , Hideaki Masuko , Yusuke Seki , Wataru Sasaki , Naoya Mashiko , Akihiro Nakano , Shin Kokura , Shoichi Ozawa , Yu Iwasaki
发明人： Toshiki Shimizu , Akira Bando , Yusaku Otsuka , Yasuhiro Kiyofuji , Elji Kobayashi , Akihiro Onozuka , Satoru Funaki , Masakazu Ishikawa , Hideaki Masuko , Yusuke Seki , Wataru Sasaki , Naoya Mashiko , Akihiro Nakano , Shin Kokura , Shoichi Ozawa , Yu Iwasaki
IPC分类号： G06F15/76 , G06F9/44 , G06F9/312
CPC分类号： G06F11/2033 , G06F8/656 , G06F11/1658 , G06F11/2028 , G06F11/2038 , G06F11/2097
摘要： The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor control system switches over either of the operation processors to be a primary operation processor that executes a control operation for a control target, and the other to be a secondary operation processor that is in a stand-by state, and the secondary operation processor snoops control data synchronously when the primary operation processor acquires the control data from the control target.
摘要翻译：本发明提供了一种双工操作处理器控制系统，其包括操作处理器，I / O设备和将操作处理器耦合到I / O设备的至少一个通信路径，以及至少一个通信路径，其将操作处理器与彼此。双工操作处理器控制系统将任一个操作处理器切换为执行控制目标的控制操作的主操作处理器，另一个作为处于待机状态的辅助操作处理器，并且次要当主操作处理器从控制目标获取控制数据时，操作处理器监听同步地控制数据。

8. 发明申请

US20080013475A1 Control Apparatus, Control Method and Control Program 有权
标题翻译：控制装置，控制方法和控制程序
公开(公告)号：US20080013475A1
公开(公告)日：2008-01-17
申请号：US11769862
申请日：2007-06-28
申请人： Akira Bandou , Masamitsu Kobayashi , Masahiro Shiraishi , Akihiro Onozuka , Takashi Umehara , Shin Kokura , Eiji Kobayashi , Masakazu Ishikawa , Yasuyuki Furuta , Naoya Mashiko , Satoru Funaki , Yuusuke Seki , Tatsuyuki Ootani , Wataru Sasaki , Yusaku Otsuka , Akihiro Nakano , Shoichi Ozawa , Takenori Kasahara , Yu Iwasaki
发明人： Akira Bandou , Masamitsu Kobayashi , Masahiro Shiraishi , Akihiro Onozuka , Takashi Umehara , Shin Kokura , Eiji Kobayashi , Masakazu Ishikawa , Yasuyuki Furuta , Naoya Mashiko , Satoru Funaki , Yuusuke Seki , Tatsuyuki Ootani , Wataru Sasaki , Yusaku Otsuka , Akihiro Nakano , Shoichi Ozawa , Takenori Kasahara , Yu Iwasaki
IPC分类号： H04B7/212
CPC分类号： G05B9/02
摘要： In a control apparatus which transmits/receives data from a central processing unit via a serial transfer channel to a communication control unit, and groups/distributes data of input/output units from the communication control unit via a parallel transfer channel, the control apparatus initiates a diagnosing unit of the parallel transfer channel in response to an instruction issued from the central processing unit, and diagnosis the input/output units subsequent to the diagnosis of the transmission channel. Data input/output timing of the input/output unit is also instructed from the central processing unit, so that the central processing unit can suppress lowering of response speeds caused by the diagnoses, and can maintain the periodicity of the data input/output.
摘要翻译：在通过串行传送信道向通信控制单元从中央处理单元发送/接收数据的控制装置中，通过并行传送信道对来自通信控制单元的输入/输出单元的数据进行分组/分配时，控制装置启动响应于从中央处理单元发出的指令，并行传输信道的诊断单元，并且诊断传输信道诊断之后的输入/输出单元。还从中央处理单元指示输入/输出单元的数据输入/输出定时，使得中央处理单元可以抑制由诊断引起的响应速度的降低，并且可以保持数据输入/输出的周期性。

9. 发明申请

US20070239916A1 Input-output control apparatus, input-output control method, process control apparatus and process control method 有权
标题翻译：输入输出控制装置，输入输出控制方法，过程控制装置和过程控制方法
公开(公告)号：US20070239916A1
公开(公告)日：2007-10-11
申请号：US11477468
申请日：2006-06-30
申请人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
发明人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
IPC分类号： G06F12/14
CPC分类号： G06F13/122 , Y02P90/14
摘要： Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
摘要翻译：通过提供输入输出控制装置，通过提供输入输出控制装置来防止输入输出装置由于处理器使用的输入输出值，以便以具有较高安全性要求的模式进行算术运算第一存储区域，存储由处理器在具有相对较低安全性要求的模式下进行算术运算的输入输出值，并将其限制在第一存储区域中，并将复制从第一存储区域区域，复制到第二存储区域，或者根据关于安全性要求的模式从第二存储区域进行复制。

10. 发明申请

US20060282702A1 Task management apparatus for control apparatus, input/output control apparatus, information control apparatus, task management method, input/output controlling method, and information controlling method 有权
标题翻译：控制装置的任务管理装置，输入输出控制装置，信息控制装置，任务管理方法，输入输出控制方法以及信息控制方法
公开(公告)号：US20060282702A1
公开(公告)日：2006-12-14
申请号：US11447724
申请日：2006-06-07
申请人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masahiro Shiraishi , Masakazu Ishikawa , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
发明人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masahiro Shiraishi , Masakazu Ishikawa , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
IPC分类号： G05B9/02 , G06F11/00
CPC分类号： G06F9/3851 , G06F9/30189 , G06F9/3885 , G06F11/1641 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F2201/845
摘要： Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.
摘要翻译：当处理器对公共对象的数据进行兼容计算时，接收到处理的结果。响应于来自任一个处理器的启动信号，生成计算命令信号并将其馈送到处理器，使得处理器可以利用不同的操作定时进行计算。然后，将处理器进行的计算的结果相互比较。因此，可以通过使用处理器的上述结构来实现同时具有小尺寸，高性能和安全性的装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式