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1. 发明申请

US20060221727A1 Semiconductor memory device and semiconductor device 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20060221727A1
公开(公告)日：2006-10-05
申请号：US11391226
申请日：2006-03-29
申请人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
发明人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
IPC分类号： G11C7/00
CPC分类号： G11C29/023 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.
摘要翻译：提供了能够通过修整半导体器件的内部特性来提高产量的技术。半导体器件具有内部降压电路和其特性值（内部电压等）可变的内部升压电路，熔丝电路单元，输入并保持来自外部的信号的JTAG功能单元304 控制电路，其基于熔丝电路单元的输出信号和JTAG功能单元的输出信号进行逻辑运算，并且控制内部降压电路和内部升压电路的特性值基于控制电路的逻辑运算的结果。

2. 发明申请

US20070274139A1 Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20070274139A1
公开(公告)日：2007-11-29
申请号：US11826751
申请日：2007-07-18
申请人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
发明人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
IPC分类号： G11C5/14
CPC分类号： G11C29/023 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.
摘要翻译：提供了能够通过修整半导体器件的内部特性来提高产量的技术。半导体器件具有内部降压电路和其特性值（内部电压等）可变的内部升压电路，熔丝电路单元，输入并保持来自外部的信号的JTAG功能单元304 控制电路，其基于熔丝电路单元的输出信号和JTAG功能单元的输出信号进行逻辑运算，并且控制内部降压电路和内部升压电路的特性值基于控制电路的逻辑运算的结果。

3. 发明授权

US07426152B2 Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US07426152B2
公开(公告)日：2008-09-16
申请号：US11826751
申请日：2007-07-18
申请人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
发明人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
IPC分类号： G11C5/14
CPC分类号： G11C29/023 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.
摘要翻译：提供了能够通过修整半导体器件的内部特性来提高产量的技术。半导体器件具有内部降压电路和其特性值（内部电压等）可变的内部升压电路，熔丝电路单元，输入并保持来自外部的信号的JTAG功能单元304 控制电路，其基于熔丝电路单元的输出信号和JTAG功能单元的输出信号进行逻辑运算，并且控制内部降压电路和内部升压电路的特性值基于控制电路的逻辑运算的结果。

4. 发明授权

US07269086B2 Semiconductor memory device and semiconductor device 有权
公开(公告)号：US07269086B2
公开(公告)日：2007-09-11
申请号：US11391226
申请日：2006-03-29
申请人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
发明人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
IPC分类号： G11C5/14
CPC分类号： G11C29/023 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.

5. 发明授权

US07123534B2 Semiconductor memory device having short refresh time 失效
标题翻译：具有短刷新时间的半导体存储器件
公开(公告)号：US07123534B2
公开(公告)日：2006-10-17
申请号：US10943895
申请日：2004-09-20
申请人： Hiroaki Nambu , Noriyuki Homma
发明人： Hiroaki Nambu , Noriyuki Homma
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/4085 , G11C11/4096 , G11C2211/4065
摘要： A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.
摘要翻译：一种半导体存储器件，其中存储器单元布置在字线和位线之间的交叉处，包括控制单元，用于在从字线中选择第一字线以进行读取的周期的后半段中进行选择或与第一字线耦合的第一存储单元的写入操作，除第一字线以外的第二字线和对应于第二字线的刷新存储单元。存储单元包括放大器部分，其包括两个驱动晶体管，栅极和漏极彼此分别交叉耦合;以及开关部分，包括根据位线上的选择信号将放大器部分与位线耦合的选择晶体管。每个晶体管和每个选择晶体管中的任一个是n沟道晶体管或p型晶体管。

6. 发明申请

US20050013160A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050013160A1
公开(公告)日：2005-01-20
申请号：US10917321
申请日：2004-08-13
申请人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
发明人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
IPC分类号： G11C8/02 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C11/00
CPC分类号： G11C11/417 , G11C11/412
摘要： Disclosed herein is a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
摘要翻译：这里公开了一种半导体存储器件，其具有包括CMOS触发器电路型存储单元的存储器阵列，其能够提高噪声容限，使得读取速度快并降低功耗。在半导体存储器件中，将存储单元的工作电压设定得高于外围电路的工作电压。构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时，构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。此外，字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。

7. 发明授权

US06369617B1 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06369617B1
公开(公告)日：2002-04-09
申请号：US09437268
申请日：1999-11-10
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为减少通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加的周期被启用。

8. 发明授权

US06316961B2 Clocked logic gate circuit 有权
公开(公告)号：US06316961B2
公开(公告)日：2001-11-13
申请号：US09725812
申请日：2000-11-30
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

9. 发明授权

US5398201A Bit-line drive circuit for a semiconductor memory 失效
标题翻译：半导体存储器的位线驱动电路
公开(公告)号：US5398201A
公开(公告)日：1995-03-14
申请号：US53330
申请日：1993-04-28
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
IPC分类号： G11C5/14 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.
摘要翻译：一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流只有写入位线才能连接。根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

10. 发明申请

US20080072095A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080072095A1
公开(公告)日：2008-03-20
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

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