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1. 发明授权

US4797583A Level converting circuit for converting voltage levels, including a current amplifying arrangement 失效
标题翻译：用于转换电压电平的电平转换电路，包括电流放大装置
公开(公告)号：US4797583A
公开(公告)日：1989-01-10
申请号：US683501
申请日：1984-12-19
申请人： Masahiro Ueno , Kozaburo Kurita , Ikuro Masuda , Nobuaki Miyakawa
发明人： Masahiro Ueno , Kozaburo Kurita , Ikuro Masuda , Nobuaki Miyakawa
IPC分类号： H03F3/45 , G11C11/409 , G11C11/416 , G11C11/419 , H03G11/00 , H03K19/0175 , H03K19/0185 , H03K19/0944 , H03K19/092 , H03K17/04 , H03K19/01 , H03K19/094
CPC分类号： H03K19/018514 , H03K19/09448
摘要： A level converter for transforming differential input voltages into an output voltage comprises a voltage-current conversion circuit for transforming the differential input voltages into differential currents, a current detection circuit for detecting the differential currents, a current amplifying circuit for amplifying the differential currents in response to the output of the current detection circuit, and a current-voltage conversion circuit for transforming the amplified differential currents into an output voltage, thereby allowing fast operation and drastic level conversion.
摘要翻译：用于将差分输入电压变换为输出电压的电平转换器包括用于将差分输入电压变换为差分电流的电压 - 电流转换电路，用于检测差分电流的电流检测电路，用于在响应中放大差分电流的电流放大电路到电流检测电路的输出，以及用于将放大的差分电流变换为输出电压的电流 - 电压转换电路，从而允许快速操作和剧烈的电平转换。

2. 发明授权

US4727517A Semiconductor memory with column line voltage sitting circuit 失效
标题翻译：半导体存储器与列线电压坐立电路
公开(公告)号：US4727517A
公开(公告)日：1988-02-23
申请号：US785654
申请日：1985-10-09
申请人： Masahiro Ueno , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Ikuro Masuda , Tetsuo Nakano
发明人： Masahiro Ueno , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Ikuro Masuda , Tetsuo Nakano
IPC分类号： G11C5/14 , G11C7/12 , G11C7/00
CPC分类号： G11C5/147 , G11C7/12
摘要： A semiconductor memory is provided including a plurality of row lines, memory cells driven by selecting a row line, sense amplifiers connected to the memory cells via column lines, and a column line voltage setting circuit for setting a predetermined voltage on the column lines. The predetermined voltage is defined by a voltage necessary to activate semiconductor switch elements constituting the column line voltage setting circuit, and is made nearly equal to the threshold voltage of the sense amplifiers. Thus, a high-speed, low power consumption semiconductor memory can be realized.
摘要翻译：提供一种半导体存储器，其包括多条行线，通过选择行线驱动的存储单元，经由列线连接到存储单元的读出放大器，以及用于在列线上设置预定电压的列线电压设置电路。预定电压由激活构成列线电压设定电路的半导体开关元件所需的电压限定，并且使其几乎等于读出放大器的阈值电压。因此，可以实现高速，低功耗的半导体存储器。

3. 发明授权

US4801983A Schottky diode formed on MOSFET drain 失效
标题翻译：在MOSFET漏极上形成肖特基二极管
公开(公告)号：US4801983A
公开(公告)日：1989-01-31
申请号：US899399
申请日：1986-08-22
申请人： Masahiro Ueno , Masahiro Iwamura , Kozaburo Kurita , Ikuro Masuda
发明人： Masahiro Ueno , Masahiro Iwamura , Kozaburo Kurita , Ikuro Masuda
IPC分类号： H03K19/0944 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/07 , H03K17/687 , H03K17/693 , H03K19/094 , H03K19/0952 , H01L27/04 , G11C11/40
CPC分类号： H03K17/687 , H01L27/0727
摘要： A unidirectional switching circuit having no charge storage effect for performing a high-speed switching operation is disclosed in which one of the anode and cathode terminals of a Schottky-barrier diode is connected to one of the source and drain terminals of a field effect transistor to form the series combination of the Schottky-barrier diode and the field effect transistor, that one of end terminals of the series combination which exists on the anode side of the diode, is used as an input terminal, the other end terminal existing on the cathode side is used as an output terminal, the gate electrode of the field effect transistor is used as a switching control electrode, and a current flowing through the switching circuit in a direction from the input terminal to the output terminal is controlled in accordance with a signal applied to the switching control electrode.
摘要翻译：公开了一种不进行高速开关动作的电荷存储效应的单向开关电路，其中肖特基势垒二极管的阳极和阴极端子之一连接到场效应晶体管的源极和漏极端子之一，形成肖特基势垒二极管和场效应晶体管的串联组合，存在于二极管的阳极侧的串联组合的端子之一用作输入端子，另一端子存在于阴极侧用作输出端子，场效应晶体管的栅电极用作开关控制电极，并且根据信号控制沿着从输入端到输出端的方向流过开关电路的电流施加到开关控制电极。

4. 发明授权

US5117382A Semiconductor integrated circuit for performing an arithmetic operation including bipolar and MOS transistors 失效
标题翻译：用于执行包括双极和MOS晶体管在内的算术运算的半导体集成电路
公开(公告)号：US5117382A
公开(公告)日：1992-05-26
申请号：US618114
申请日：1990-11-26
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

5. 发明授权

US4200225A Diagnostic check system for digital signal circuit 失效
标题翻译：数字信号电路诊断检查系统
公开(公告)号：US4200225A
公开(公告)日：1980-04-29
申请号：US912316
申请日：1978-06-05
申请人： Masahiro Ueno , Ikuro Masuda
发明人： Masahiro Ueno , Ikuro Masuda
IPC分类号： H04L1/00 , G05B19/048 , G05B23/02 , G06F11/00 , G06F11/27 , G06F11/30 , G01R31/28
CPC分类号： G06F11/27 , G05B19/048
摘要： A diagnostic check system for a digital signal circuit, in which, in a state where a plurality of digital signals are being sent out from a processor such as a microcomputer through an interface and photo-coupling elements to a controlled apparatus, the processor periodically processes all the digital signals to simultaneously cause them to be the same signal mode "1" or "0" for a period of time that is too short for the controlled apparatus to respond to the change in the levels of the digital signals, and the processor also detects whether the modes of all the signals transferred from the photo-coupling elements to the controlled apparatus for the short period of time are coincident or not.
摘要翻译：一种用于数字信号电路的诊断检查系统，其中在通过接口和光耦合元件从诸如微计算机的处理器发送多个数字信号到受控设备的状态下，处理器周期性地处理所有的数字信号同时使它们在受控设备对数字信号电平的变化作出响应的时间太短的时间段内处于相同的信号模式“1”或“0”，并且处理器还检测在短时间内从光耦合元件传送到受控设备的所有信号的模式是否一致。

6. 发明授权

US4789958A Carry-look-ahead adder including bipolar and MOS transistors 失效
标题翻译：携带前视加法器包括双极和MOS晶体管
公开(公告)号：US4789958A
公开(公告)日：1988-12-06
申请号：US703171
申请日：1985-02-19
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.
摘要翻译：提供了作为半导体集成电路实现的进位前视加法器。集成电路包括耦合到输出端的双极晶体管，用于提供表示算术运算的输出。阻抗元件耦合到双极晶体管，并且提供至少一个FET以控制双极晶体管的导通/截止状态。

7. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

8. 发明授权

US5153452A Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效
标题翻译：具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC
公开(公告)号：US5153452A
公开(公告)日：1992-10-06
申请号：US401849
申请日：1989-08-30
申请人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/56 , H01L21/822 , H01L27/06
CPC分类号： G11C11/565 , G05F1/465 , G11C5/147 , G11C16/30
摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.
摘要翻译：提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。

9. 发明授权

US5042010A Semiconductor integrated circuit 失效
公开(公告)号：US5042010A
公开(公告)日：1991-08-20
申请号：US520620
申请日：1990-05-08
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and lower power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portiosn of the circuit use CMOS elements of lower power consumption. This arrangement is particulary advantageous in memory circuits.

10. 发明授权

US4924439A Semiconductor integrated circuit 失效
公开(公告)号：US4924439A
公开(公告)日：1990-05-08
申请号：US358262
申请日：1989-05-30
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

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