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1. 发明授权

US5214680A CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration 失效
标题翻译： CMOS伪NMOS可编程电容时间游标和校准方法
公开(公告)号：US5214680A
公开(公告)日：1993-05-25
申请号：US786447
申请日：1991-11-01
申请人： Alberto Gutierrez, Jr. , Christopher Koerner , Masaharu Goto , James O. Barnes
发明人： Alberto Gutierrez, Jr. , Christopher Koerner , Masaharu Goto , James O. Barnes
IPC分类号： G01R31/319 , H03K5/00 , H03K5/13 , H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/687 , G01R31/31922 , H03K5/131 , H03K5/133 , H03M1/66 , H03K2005/00097 , H03M1/745 , H03M1/747
摘要： The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges. Furthermore, the architecture of the present invention enables an automated method of calibration in order to adjust fine and coarse delay elements for fabrication process variations and photolithography variations.
摘要翻译：本发明是提供具有粗定时边缘的输入信号的精确定时控制的时间游标。时间游标包括接收装置，用于接收表示要添加到粗时序边缘输入的期望时间延迟的值。期望的时间延迟可以具有精细和粗略的延迟方面。时间游标还包括用于解码精细延迟方面并产生精细延迟控制信号的第一解码装置，以及用于解码粗略延迟方面并产生粗略延迟控制信号的第二解码装置。延时线还包括在时间游标中，其具有用于接收具有粗定时边缘的输入信号的输入，精细和粗略的延迟控制信号以及根据温度和电源变化自动调整的控制电压，以便提供温度和电源补偿。延迟线组合精细和粗略的延迟信号，以提供具有精细时序边缘的输出信号。此外，本发明的架构能够实现自动校准方法，以便调整用于制造工艺变化和光刻变化的精细和粗略的延迟元件。

2. 发明授权

US5324916A System and method for dynamic power compensation 失效
标题翻译：动态功率补偿系统和方法
公开(公告)号：US5324916A
公开(公告)日：1994-06-28
申请号：US786655
申请日：1991-11-01
申请人： Masaharu Goto , Christopher Koerner
发明人： Masaharu Goto , Christopher Koerner
IPC分类号： G06F15/78 , G05D23/20 , H01L23/34 , H01L23/58 , H03F1/52 , H03K19/003 , H05B1/02 , H05B1/00
CPC分类号： H01L23/345 , G05D23/1906 , G05D23/20 , H01L2924/0002 , H01L2924/3011
摘要： A system and method for compensating in real time the dynamic power variation of a computer chip containing CMOS devices is provided. The present invention functions to control the temperature variations on the chip thus eliminating the drift to analog signals associated with CMOS devices. The present invention controls the temperature with the use of a compensation heater located on the CMOS chip. The compensation heater is driven by a plurality of signals which act in harmony with one another to control the temperature on the chip when it becomes unstable. The system and method includes driving the compensation heater with a maximum dynamic power value to effectively maintain the temperature on the chip, evaluating the chip for temperature fluctuation, and compensating for the temperature fluctuation by driving the compensation heater with at least one compensation power value.
摘要翻译：提供一种用于实时补偿包含CMOS器件的计算机芯片的动态功率变化的系统和方法。本发明用于控制芯片上的温度变化，从而消除了与CMOS器件相关的模拟信号的漂移。本发明通过使用位于CMOS芯片上的补偿加热器来控制温度。补偿加热器由多个彼此协调的信号驱动，以在芯片变得不稳定时控制芯片上的温度。该系统和方法包括以最大动态功率值驱动补偿加热器，以有效地保持芯片上的温度，评估芯片的温度波动，并通过以至少一个补偿功率值驱动补偿加热器来补偿温度波动。

3. 发明授权

US5233637A System for generating an analog regulating voltage 失效
标题翻译：用于产生模拟调节电压的系统
公开(公告)号：US5233637A
公开(公告)日：1993-08-03
申请号：US786690
申请日：1991-11-01
申请人： Christopher Koerner , Alberto Gutierrez, Jr. , James O. Barnes , James R. Hulings
发明人： Christopher Koerner , Alberto Gutierrez, Jr. , James O. Barnes , James R. Hulings
IPC分类号： G01R31/28 , G01R31/319 , H03K5/00 , H03K5/13 , H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： G01R31/31922 , G01R31/2841 , H03K5/131 , H03K5/133 , H03M1/66 , H03M1/687 , H03K2005/00097 , H03M1/745 , H03M1/747
摘要： A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a property of changing with temperature, power supply voltage, and manufacturing process variations so as to substantially eliminate the effects of such variations on the operational characteristics of the circuit elements.
摘要翻译：一种用于产生要提供给集成电路上的一个或多个电路元件的模拟调节电压的系统。电路元件具有与电压相关的操作特性，并且具有随着温度，电源电压和制造工艺变化而变化的性质的模拟调节电压，从而基本上消除了这种变化对电路元件的操作特性的影响。

4. 发明授权

US06223242B1 Linearly expandable self-routing crossbar switch 有权
标题翻译：线性可扩展自路交叉开关
公开(公告)号：US06223242B1
公开(公告)日：2001-04-24
申请号：US09161923
申请日：1998-09-28
申请人： Stephen J. Sheafor , Christopher Koerner , Bradford C. Lincoln , Robert Sugar , Jonathan L. Huie
发明人： Stephen J. Sheafor , Christopher Koerner , Bradford C. Lincoln , Robert Sugar , Jonathan L. Huie
IPC分类号： G06F1300
CPC分类号： H04L49/25 , H04L49/101 , H04L49/1538 , H04L49/45
摘要： A crossbar routing arrangement is disclosed for use in a digital system having three or more buses. An associated method is also disclosed. The routing arrangement is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses and includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self-routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. The control arrangement cooperates with the switching arrangement to transfer the data subsets over physically distinct data transfer paths defined between the switching arrangement and the control arrangements. In accordance with one feature, the configuration of the routing arrangement provides for linear expansion whereby to service buses having increased width and/or to service an increased number of buses in a cost effective manner while, in either instance, maintaining high data throughput.
摘要翻译：公开了一种用于具有三个或更多个总线的数字系统中的横梁路由布置。还公开了一种相关联的方法。路由布置被配置为将从总线中的任何特定一个总线接收的一组数据传送到总线中的任何其他所选择的总线，并且包括与每个总线相关联的控制装置，用于将该组数据分成至少第一和第二子集数据和用于将每个数据子集添加自路由信号，信号标识所选择的总线。交换装置被配置为响应于自路由信号以预定方式引导第一和第二数据子集。控制装置与切换装置配合以将数据子集传送到在切换装置和控制装置之间限定的物理不同的数据传输路径上。根据一个特征，路由布置的配置提供线性扩展，从而以成本有效的方式服务具有增加的宽度和/或服务于增加数量的总线的总线，而在任一情况下维持高数据吞吐量。

5. 发明授权

US5283631A Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations 失效
标题翻译：可编程电容延迟元件具有由可调电压控制的逆变器，以抵消温度和电压供应变化
公开(公告)号：US5283631A
公开(公告)日：1994-02-01
申请号：US786633
申请日：1991-11-01
申请人： Christopher Koerner , Alberto Gutierrez, Jr. , Edward G. Pumphrey
发明人： Christopher Koerner , Alberto Gutierrez, Jr. , Edward G. Pumphrey
IPC分类号： G01R31/28 , G01R31/319 , H03K5/00 , H03K5/13 , H03M1/66 , H03M1/68 , H03M1/74 , H03K19/20
CPC分类号： H03K5/131 , G01R31/2841 , G01R31/31922 , H03K5/133 , H03M1/66 , H03M1/687 , H03K2005/00097 , H03M1/745 , H03M1/747
摘要： A delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output. The delay element further comprises a node comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node. Finally, the variable capacitance means is connected to the node for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal propagating from the first inverter to the second inverter.
摘要翻译：一种用于在输入信号的定时边沿的时间内微调位置的延迟元件，包括第一和第二发明者，每个包括数据输入，控制输入和数据输出。延迟元件还包括由第一反相器的数据输出与第二反相器的数据输入之间的连接构成的节点。包括可调整的控制电压，以将偏置电压施加到第一和第二控制输入，从而控制提供给节点的电荷量。最后，可变电容装置连接到节点，用于向节点施加有限量的电容以延迟，从而在时间上微调从第一逆变器传播到第二逆变器的输入信号的定时边缘。

6. 发明授权

US5041831A Indirect D/A converter 失效
标题翻译：间接D / A转换器
公开(公告)号：US5041831A
公开(公告)日：1991-08-20
申请号：US186311
申请日：1988-04-26
申请人： Thomas K. Bohley , Grosvenor H. Garnett , Christopher Koerner
发明人： Thomas K. Bohley , Grosvenor H. Garnett , Christopher Koerner
IPC分类号： H03M1/66 , H03M1/00
CPC分类号： H03M1/662 , H03M1/1014 , H03M1/822
摘要： A plural channel indirect digital to analog converter. Words containing address bits and data bits are received on an input and entered into a specific one of the converter channels under control of the address bits of the word. The data bits are applied to a binary rate multiplier of the channel which generates a pulse modulated output signal representing the binary value of the received data bits. The pulse modulated output signal is applied to an associated filter which converts the pulse modulated signal to an analog output signal whose amplitude represents the binary value of the received data bits. Gating circuitry ensures that each output pulse is of a precisely controlled pulse width. One of the converter channels is used to calibrate the output level of the filters. The number of data bits applied to the different channels may need not be the same and may vary in number from a minimum of 1 to a maximum of m.

7. 发明授权

US5712539A Digital acoustic noise reduction in electric motors driven by switching power amplifiers 失效
标题翻译：由开关功率放大器驱动的电动机中的数字声学降噪
公开(公告)号：US5712539A
公开(公告)日：1998-01-27
申请号：US483521
申请日：1995-06-07
申请人： James Zweighaft , Mark H. Moyer , Christopher Koerner
发明人： James Zweighaft , Mark H. Moyer , Christopher Koerner
IPC分类号： H02P6/14 , H02P6/00 , B65H59/38 , H02P7/01
CPC分类号： H02P6/14
摘要： A system and method is provided for controlling a brushless DC motor (100), the motor being of the type having a plurality of coils (25, 26, 27) and a switching amplifier coil driving circuit (25A, 26A, 27A) including a plurality of transistors (21, 22, 29, 30, 33, 34). Current application to the plurality of transistors is controlled to obtain, near a commutation point of the motor, a simultaneous rise in current applied to a first of the transistors and a fall in current applied to a second of the transistors. Controlling application of current to the plurality of transistors involves, for each of the transistors, generating a PWM gate drive signal by selectively switching between a nominal PWM signal and a constant signal. The selective switching is in response to a synthesized state signal, the synthesized state signal being generated to alternate variably between the two states in accordance with a desired ramping of current to the first and second transistors. In one embodiment, the control system is employed for a motor used to rotate a reel of a helical scan tape drive.
摘要翻译：提供了一种用于控制无刷直流电动机（100）的系统和方法，所述电动机是具有多个线圈（25,26,27）的类型和包括一个线圈的开关放大器线圈驱动电路（25A，26A，27A）多个晶体管（21,22,29,30,33,34）。控制对多个晶体管的当前应用以在电动机的换向点附近获得施加到第一晶体管的电流的同时上升和施加到第二晶体管的电流的下降。控制对多个晶体管的电流的施加涉及通过选择性地在标称PWM信号和恒定信号之间切换来产生PWM栅极驱动信号的每个晶体管。选择性切换响应于合成状态信号，根据期望的向第一和第二晶体管的电流斜坡，产生合成状态信号以在两个状态之间交替变化。在一个实施例中，控制系统被用于用于旋转螺旋扫描带驱动器的卷轴的马达。

8. 发明授权

US5243227A Fine/coarse wired-or tapped delay line 失效
标题翻译：精细/粗糙的有线或抽头延迟线
公开(公告)号：US5243227A
公开(公告)日：1993-09-07
申请号：US786459
申请日：1991-11-01
申请人： Alberto Gutierrez, Jr. , Christopher Koerner
发明人： Alberto Gutierrez, Jr. , Christopher Koerner
IPC分类号： G01R31/28 , G01R31/319 , H03K5/00 , H03K5/13 , H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03K5/131 , G01R31/2841 , G01R31/31922 , H03K5/133 , H03M1/66 , H03M1/687 , H03K2005/00097 , H03M1/745 , H03M1/747
摘要： The present invention is directed to a delay line for providing fine timing adjustment on subsequent edges of an input signal. The delay line comprises a plurality of delay elements for fine tuning the position in time of the timing edges of the input signal. Each delay element has a data input and data output where the data output is connected to the subsequent delay element's data input, thereby forming a delay line with delay elements connected in series. This implementation facilitates the addition of fine increments of delay to be added to the input signal and thereby enable fine tuning of timing edges. Also, included is a wired-OR multiplexor having data inputs connected to the data outputs of the plurality of the delay elements and a control input to select a particular data output to thereby provide an output signal having delayed timing edges.
摘要翻译：本发明涉及一种用于在输入信号的后续边缘上提供精细定时调整的延迟线。延迟线包括多个延迟元件，用于在输入信号的定时边缘的时间内微调该位置。每个延迟元件具有数据输入和数据输出，其中数据输出连接到后续延迟元件的数据输入，从而形成具有串联连接的延迟元件的延迟线。该实施方式有助于增加要添加到输入信号的延迟的精细增量，从而实现定时边缘的微调。此外，包括有线或有效多路复用器，其具有连接到多个延迟元件的数据输出的数据输入和用于选择特定数据输出的控制输入，从而提供具有延迟定时边缘的输出信号。

9. 发明授权

US4940979A Combined rate/width modulation arrangement 失效
标题翻译：组合速率/宽度调制方案
公开(公告)号：US4940979A
公开(公告)日：1990-07-10
申请号：US186430
申请日：1988-04-26
申请人： Thomas K. Bohley , Grosvenor H. Garnett , Christopher Koerner , Charles E. Moore
发明人： Thomas K. Bohley , Grosvenor H. Garnett , Christopher Koerner , Charles E. Moore
IPC分类号： H03M1/82 , H03M1/00
CPC分类号： H03M1/68 , H03M1/822 , H03M1/86
摘要： Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.

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