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1. 发明申请

US20050105309A1 Current/charge-voltage convertor 有权
标题翻译：电流/充电电压转换器
公开(公告)号：US20050105309A1
公开(公告)日：2005-05-19
申请号：US10982209
申请日：2004-11-05
申请人： Tomoya Fujisaki , Masaharu Goto
发明人： Tomoya Fujisaki , Masaharu Goto
IPC分类号： G01R19/00 , G01R29/24 , G06G7/186 , H02M7/00 , H03F3/00
CPC分类号： G01R29/24 , G01R19/0092
摘要： A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.
摘要翻译：一种具有运算放大器和连接在运算放大器的输入端和输出端之间的电容器的电流/电荷 - 电压转换电路，该电流/电荷 - 电压转换电路的特征在于，它包括相互连接的第一对二极管与该输入端相反的方向，将第二对二极管与该第一对二极管的相反方向连接到该第一对二极管的相应另一个端子，一对电流源以相互相对的方向连接到相应的另一个端子的第一对二极管，连接到该第一对二极管的另一个端子的一对开关，以及连接在该第二对二极管的相应另一个端子之间的电阻器。

2. 发明授权

US5589788A Timing adjustment circuit 失效
标题翻译：定时调整电路
公开(公告)号：US5589788A
公开(公告)日：1996-12-31
申请号：US435877
申请日：1995-05-05
申请人： Masaharu Goto
发明人： Masaharu Goto
IPC分类号： G01R29/02 , G01R31/00 , G01R31/3183 , G01R31/319 , G06F1/10 , H03K5/13 , H03K5/135
CPC分类号： G01R31/3191 , H03K5/131
摘要： A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements. When the active edge has arrived at each of the selection gates, each is held in an output state until the input to the selection gates becomes inactive, even if the selection signals changes.
摘要翻译：定时调整电路包括由串联连接的n个延迟元件（n为2以上的整数）构成的延迟电路，输入信号p0由各个延迟元件依次延迟，以产生相应的延迟元件，信号p1，。。。，pn以及输入信号p0和上述各个延迟信号p1，...的选择电路。。。，pn由n + 1个选择信号s0，...选择。。。，sn。选择电路包括选择信号生成电路，选择门电路，选择信号保持电路和延迟信号保持电路。选择信号生成电路生成选择信号s0，...。。。，输入信号p0之前的sn。选择信号保持电路保持选择信号s0，。。。，sn从选择信号发生电路直到p0的有效边沿。。。，pn到达每个选择门。延迟信号保持电路包括n个延迟信号保持元件。当有效边沿到达每个选择门时，即使选择信号改变，每个选择门都保持在输出状态，直到选择门的输入变为无效。

3. 发明授权

US08857747B2 Food preparation device 有权
标题翻译：食物制备装置
公开(公告)号：US08857747B2
公开(公告)日：2014-10-14
申请号：US13374758
申请日：2012-01-10
申请人： Masaharu Goto
发明人： Masaharu Goto
IPC分类号： A47J43/25
CPC分类号： A47J43/25
摘要： A food preparation plate is replaceable and engagement means for retaining the food preparation plate are present between the food preparation plate and a retaining part. The food preparation plate can move in translation in a direction perpendicular to a plane constituted by the retaining part. Two places on the back side of the food preparation plate that is retained in the retaining part can be simultaneously pressed in the direction of the front side by the digits of different hands; and by simultaneously pressing those two places with digits of different hands, the food preparation plate is moved in translation in the direction of the front side thereof, so as to release the engagement means and allow the food preparation plate to be detached.
摘要翻译：食品准备板是可替换的，并且用于保持食物制备板的接合装置存在于食物准备板和保持部分之间。食物准备板可以在垂直于由保持部构成的平面的方向上平移移动。保持在保持部上的食品准备板的背侧的两个位置可以通过不同的手的数字同时沿前侧的方向按压; 并且通过同时用不同手的数字按压这两个位置，使食物准备板沿其前侧的方向移动平移，以便释放接合装置并允许食物准备板被拆卸。

4. 发明授权

US06415778B1 Breather chamber structure of internal combustion engine 有权
标题翻译：内燃机呼吸室结构
公开(公告)号：US06415778B1
公开(公告)日：2002-07-09
申请号：US09807957
申请日：2001-07-19
申请人： Hiroyuki Makino , Masaharu Goto , Yasuyo Kosugi , Shotaro Takano
发明人： Hiroyuki Makino , Masaharu Goto , Yasuyo Kosugi , Shotaro Takano
IPC分类号： F02M3510
CPC分类号： F01M13/04 , F01M5/021 , F01M2013/0027 , F01M2013/0455 , F01M2013/0472
摘要： A breather chamber structure of an internal combustion engine in which condensation of vapor within the breather chamber is prevented, the number of required parts is small, the space efficiency is superior and enlargement of the whole engine can be avoided is provided. In an internal combustion engine having auxiliary machinery attached to a side wall of a cylinder block (3) by means of an auxiliary machinery bracket (10), a breather chamber (20) is formed by the side wall of the cylinder block (3) and the auxiliary machinery bracket (10) between the side wall and the bracket, and a cooling water passage (40), (41) is formed on at least one of the side wall of the cylinder block (3) and the auxiliary machinery bracket (10) swelling in the breather chamber (20).
摘要翻译：一种内燃机的通气室结构，其中防止了通气室内的蒸汽冷凝，所需部件的数量小，空间效率优异，并且可以避免整个发动机的放大。在内燃具有通过辅助机械支架（10）附接到气缸体（3）的侧壁的辅助机械的发动机，通过气缸体（3）的侧壁和辅助机构形成的通气室（20）在侧壁和支架之间的支架（10）和在气缸体（3）的侧壁和辅助机械支架（10）中的至少一个上形成有膨胀的冷却水通道（40），（41）在通气室（20）中。

5. 发明授权

US5324916A System and method for dynamic power compensation 失效
标题翻译：动态功率补偿系统和方法
公开(公告)号：US5324916A
公开(公告)日：1994-06-28
申请号：US786655
申请日：1991-11-01
申请人： Masaharu Goto , Christopher Koerner
发明人： Masaharu Goto , Christopher Koerner
IPC分类号： G06F15/78 , G05D23/20 , H01L23/34 , H01L23/58 , H03F1/52 , H03K19/003 , H05B1/02 , H05B1/00
CPC分类号： H01L23/345 , G05D23/1906 , G05D23/20 , H01L2924/0002 , H01L2924/3011
摘要： A system and method for compensating in real time the dynamic power variation of a computer chip containing CMOS devices is provided. The present invention functions to control the temperature variations on the chip thus eliminating the drift to analog signals associated with CMOS devices. The present invention controls the temperature with the use of a compensation heater located on the CMOS chip. The compensation heater is driven by a plurality of signals which act in harmony with one another to control the temperature on the chip when it becomes unstable. The system and method includes driving the compensation heater with a maximum dynamic power value to effectively maintain the temperature on the chip, evaluating the chip for temperature fluctuation, and compensating for the temperature fluctuation by driving the compensation heater with at least one compensation power value.
摘要翻译：提供一种用于实时补偿包含CMOS器件的计算机芯片的动态功率变化的系统和方法。本发明用于控制芯片上的温度变化，从而消除了与CMOS器件相关的模拟信号的漂移。本发明通过使用位于CMOS芯片上的补偿加热器来控制温度。补偿加热器由多个彼此协调的信号驱动，以在芯片变得不稳定时控制芯片上的温度。该系统和方法包括以最大动态功率值驱动补偿加热器，以有效地保持芯片上的温度，评估芯片的温度波动，并通过以至少一个补偿功率值驱动补偿加热器来补偿温度波动。

6. 发明授权

US5280195A Timing generator 失效
标题翻译：定时发生器
公开(公告)号：US5280195A
公开(公告)日：1994-01-18
申请号：US837350
申请日：1992-02-14
申请人： Masaharu Goto , Koh Murata , Nobuyuki Kasuga
发明人： Masaharu Goto , Koh Murata , Nobuyuki Kasuga
IPC分类号： G06F1/06 , H03K5/13 , H03K5/133 , H03K01/17
CPC分类号： H03K5/131 , H03K5/133
摘要： A timing generator having no dead time and capable of altering a timing at any time. A rough timing pulse generating means suitably specifies one of a plurality of input clock pulses to generate a rough timing pulse for a desired timing. A timing vernier delays the rough timing pulse for a suitable delay time to generate a minute timing pulse. In a compensating circuit, the minute timing pulse is input to a delay circuit having one input terminal and plural output terminals, and one of the outputs at the output terminals for delay is selected by a multiplexer. When the multiplexer selects an output whose delay time is not zero, a next pulse can be input from the timing vernier to the dead time compensating circuit so that no dead time occurs.
摘要翻译：具有无死区时间并能随时更改定时的定时发生器。粗略定时脉冲发生装置适当地指定多个输入时钟脉冲之一以产生期望定时的粗略定时脉冲。定时游标将粗略的定时脉冲延迟适当的延迟时间以产生微小的定时脉冲。在补偿电路中，分时定时脉冲被输入到具有一个输入端和多个输出端的延迟电路，并且在多路复用器选择用于延迟的输出端的输出之一。当多路复用器选择延迟时间不为零的输出时，可以从定时游标器输入下一个脉冲到死区补偿电路，从而不会发生死区时间。

7. 发明授权

US07404130B2 Method for optimizing a pattern generation program, a program, and a signal generator 失效
标题翻译：用于优化图案生成程序，程序和信号发生器的方法
公开(公告)号：US07404130B2
公开(公告)日：2008-07-22
申请号：US11181955
申请日：2005-07-14
申请人： Masaru Shimura , Takuya Otani , Masaharu Goto
发明人： Masaru Shimura , Takuya Otani , Masaharu Goto
IPC分类号： G01R31/28 , G06F9/44
CPC分类号： G01R31/31813 , G01R31/318314
摘要： A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, this optimizing method comprising an evaluation step for evaluating for each command of the pattern generation program whether it is necessary to develop the command in question of the program and a development step for developing the command.
摘要翻译：一种用于优化在信号发生器中使用的模式生成程序的方法，包括：发生器，用于基于模式产生程序产生信号模式;存储器，用于存储信号模式;以及输出，用于以预定周期输出由存储器，该优化方法包括用于评估图案生成程序的每个命令的评估步骤，是否需要开发所述程序的问题的命令以及用于开发命令的开发步骤。

8. 发明授权

US07057909B2 Current/charge-voltage converter 有权
标题翻译：电流/电荷电压转换器
公开(公告)号：US07057909B2
公开(公告)日：2006-06-06
申请号：US10982209
申请日：2004-11-05
申请人： Tomoya Fujisaki , Masaharu Goto
发明人： Tomoya Fujisaki , Masaharu Goto
IPC分类号： H02M7/00
CPC分类号： G01R29/24 , G01R19/0092
摘要： A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.
摘要翻译：一种具有运算放大器和连接在运算放大器的输入端和输出端之间的电容器的电流/电荷 - 电压转换电路，该电流/电荷 - 电压转换电路的特征在于，它包括相互连接的第一对二极管与该输入端相反的方向，将第二对二极管与该第一对二极管的相反方向连接到该第一对二极管的相应另一个端子，一对电流源以相互相对的方向连接到相应的另一个端子的第一对二极管，连接到该第一对二极管的另一个端子的一对开关，以及连接在该第二对二极管的相应另一个端子之间的电阻器。

9. 发明授权

US5712855A Apparatus for testing and measuring electronic device and method of calibrating its timing and voltage level 失效
标题翻译：用于测试和测量电子设备的装置及其时序和电压电平校准方法
公开(公告)号：US5712855A
公开(公告)日：1998-01-27
申请号：US145419
申请日：1993-10-29
申请人： Masaharu Goto , Kenichi Ito
发明人： Masaharu Goto , Kenichi Ito
IPC分类号： G01R31/00 , G01R31/28 , G01R31/319 , G01R35/00 , G06K5/04 , G11B27/00
CPC分类号： G01R35/00 , G01R31/3191
摘要： The present invention is intended to provide a testing and measuring apparatus for accurately and quickly calibrating the input and output timing of a plurality of test signal patterns and voltage levels. The invention also offers a method used for the calibration. The apparatus is equipped with a plurality of units (timing vector generators) each having a timing-generating circuit (a capture timing generator) and an external common reference timing circuit (a golden edge generator) outside the units. Each unit comprises: (1) a timing comparator circuit (a capture comparator) for comparing the timing each of the timing-generating circuits with the timing of the reference timing circuit to determine whether the former timing leads or lags the latter timing; and (2) a counter circuit which counts a number of comparisons made by the comparator circuit until their sequential relation has been reversed.
摘要翻译：本发明旨在提供一种用于准确且快速地校准多个测试信号模式和电压电平的输入和输出定时的测试和测量装置。本发明还提供了用于校准的方法。该装置配备有在单元外部具有定时发生电路（捕获定时发生器）和外部公共基准定时电路（金边缘发生器）的多个单元（定时矢量发生器）。每个单元包括：（1）定时比较器电路（捕获比较器），用于将每个定时产生电路的定时与基准定时电路的定时进行比较，以确定前一个时序是否导通或落后于后一个定时; 以及（2）计数器电路，对由比较器电路进行的比较进行计数，直到它们的顺序关系被反转。

10. 发明授权

US5214680A CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration 失效
标题翻译： CMOS伪NMOS可编程电容时间游标和校准方法
公开(公告)号：US5214680A
公开(公告)日：1993-05-25
申请号：US786447
申请日：1991-11-01
申请人： Alberto Gutierrez, Jr. , Christopher Koerner , Masaharu Goto , James O. Barnes
发明人： Alberto Gutierrez, Jr. , Christopher Koerner , Masaharu Goto , James O. Barnes
IPC分类号： G01R31/319 , H03K5/00 , H03K5/13 , H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/687 , G01R31/31922 , H03K5/131 , H03K5/133 , H03M1/66 , H03K2005/00097 , H03M1/745 , H03M1/747
摘要： The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges. Furthermore, the architecture of the present invention enables an automated method of calibration in order to adjust fine and coarse delay elements for fabrication process variations and photolithography variations.
摘要翻译：本发明是提供具有粗定时边缘的输入信号的精确定时控制的时间游标。时间游标包括接收装置，用于接收表示要添加到粗时序边缘输入的期望时间延迟的值。期望的时间延迟可以具有精细和粗略的延迟方面。时间游标还包括用于解码精细延迟方面并产生精细延迟控制信号的第一解码装置，以及用于解码粗略延迟方面并产生粗略延迟控制信号的第二解码装置。延时线还包括在时间游标中，其具有用于接收具有粗定时边缘的输入信号的输入，精细和粗略的延迟控制信号以及根据温度和电源变化自动调整的控制电压，以便提供温度和电源补偿。延迟线组合精细和粗略的延迟信号，以提供具有精细时序边缘的输出信号。此外，本发明的架构能够实现自动校准方法，以便调整用于制造工艺变化和光刻变化的精细和粗略的延迟元件。

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