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    • 1. 发明授权
    • System and method for adjusting a sampling time in a logic analyzer
    • 用于调整逻辑分析仪中采样时间的系统和方法
    • US06463392B1
    • 2002-10-08
    • US09375307
    • 1999-08-16
    • Richard A. NygaardEdward G. PumphreyKeith C. Griggs
    • Richard A. NygaardEdward G. PumphreyKeith C. Griggs
    • G01D1800
    • G01R31/31937
    • A system and method are provided for detecting a stable region in a data signal to facilitate the alignment between a data signal and a corresponding clock signal. The system includes a processor coupled to a local interface and a memory coupled to the local interface. The system also includes a boundary detection circuit configured to perform a simultaneous sampling of a reference signal and a delayed reference signal to ascertain a degree of stability of a position in the reference signal. The reference signal is the signal received from the target system and the delayed reference signal is a delayed copy of the reference signal. The system also includes boundary detection logic stored on the memory and executed by the processor to control the operation of the boundary detection circuit. The boundary detection logic includes logic to detect a boundary of the stable region of the reference.
    • 提供了一种用于检测数据信号中的稳定区域以促进数据信号与对应的时钟信号之间的对准的系统和方法。 该系统包括耦合到本地接口的处理器和耦合到本地接口的存储器。 该系统还包括边界检测电路,其被配置为执行参考信号和延迟参考信号的同时采样,以确定参考信号中的位置的稳定度。 参考信号是从目标系统接收的信号,延迟的参考信号是参考信号的延迟拷贝。 该系统还包括存储在存储器中并由处理器执行以控制边界检测电路的操作的边界检测逻辑。 边界检测逻辑包括检测参考的稳定区域的边界的逻辑。