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1. 发明授权

US07024446B2 Circuitry for arithmetically accumulating a succession of arithmetic values 失效
标题翻译：用于算术累积一系列算术值的电路
公开(公告)号：US07024446B2
公开(公告)日：2006-04-04
申请号：US10625093
申请日：2003-07-22
申请人： Martin Langhammer , Nitin Prasad
发明人： Martin Langhammer , Nitin Prasad
IPC分类号： G06F7/50
CPC分类号： G06F7/5095 , G06F5/015 , G06F7/53 , G06F7/575 , G06F7/724 , G06F15/7867 , G06F2207/3828 , H03K19/177 , H03K19/17732 , H03K19/17736
摘要： A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.
摘要翻译：可编程逻辑集成电路器件除了可编程逻辑的通常多个区域和通常的可编程逻辑器件之外，还具有至少一个功能特定电路块（例如，并行乘法器，并行桶形移位器，并行算术逻辑单元等）互联电路资源。为了减少使用功能特定块（“FSB”）对设备的通用互连资源的影响，FSB的输入和/或输出可以相对直接地耦合到逻辑区域的子集。除了节省通用互连之外，FSB可以使用FSB连接的逻辑区域的资源，以减少必须专用于FSB的电路的数量。如果FSB是乘法器，则附加特征包括促进连续乘法器输出的累积（如果需要，使用加法或减法和符号扩展）和/或算术组合多个乘法器的输出。

2. 发明申请

US20050187999A1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US20050187999A1
公开(公告)日：2005-08-25
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/499 , G06F7/52 , G06F7/523 , G06F7/544
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

3. 发明授权

US08615543B1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US08615543B1
公开(公告)日：2013-12-24
申请号：US13166119
申请日：2011-06-22
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

4. 发明授权

US08209545B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08209545B1
公开(公告)日：2012-06-26
申请号：US12785400
申请日：2010-05-21
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： H04L9/08
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

5. 发明授权

US07660841B2 Flexible accumulator in digital signal processing circuitry 失效
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US07660841B2
公开(公告)日：2010-02-09
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

6. 发明授权

US07467176B2 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US07467176B2
公开(公告)日：2008-12-16
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在乘法累加（MAC）块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

7. 发明申请

US20090100122A1 SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS 审中-公开
标题翻译：多重积累块中的饱和和饱和度
公开(公告)号：US20090100122A1
公开(公告)日：2009-04-16
申请号：US12324055
申请日：2008-11-26
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC模块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累积电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

8. 发明授权

US06628140B2 Programmable logic devices with function-specific blocks 有权
公开(公告)号：US06628140B2
公开(公告)日：2003-09-30
申请号：US09924354
申请日：2001-08-07
申请人： Martin Langhammer , Nitin Prasad
发明人： Martin Langhammer , Nitin Prasad
IPC分类号： H03K19177
CPC分类号： G06F7/5095 , G06F5/015 , G06F7/53 , G06F7/575 , G06F7/724 , G06F15/7867 , G06F2207/3828 , H03K19/177 , H03K19/17732 , H03K19/17736
摘要： A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.

9. 发明授权

US09170775B2 Flexible accumulator in digital signal processing circuitry 有权
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US09170775B2
公开(公告)日：2015-10-27
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

10. 发明授权

US08826038B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08826038B1
公开(公告)日：2014-09-02
申请号：US13474745
申请日：2012-05-18
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F21/00
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

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