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1. 发明授权

US06654924B1 System and method for error correction of digitized phase signals from MR/GMR head readback waveforms 失效
标题翻译：用于MR / GMR头回读波形数字化相位信号纠错的系统和方法
公开(公告)号：US06654924B1
公开(公告)日：2003-11-25
申请号：US09675857
申请日：2000-09-29
申请人： Martin Aureliano Hassner , Francesco Rezzi , Barry Marshall Trager
发明人： Martin Aureliano Hassner , Francesco Rezzi , Barry Marshall Trager
IPC分类号： H03M1300
CPC分类号： H03M13/095 , G11B20/1813 , H03M5/145 , H03M13/39
摘要： A system and method for algebraically correcting errors in complex digitized phase signals from a magneto-resistive or giant magneto-resistive (MR/GMR) head readback waveform includes a data state machine that encodes phase symbols into data bits in accordance with, e.g., the (1, 10) constraint and a parity state machine that generates parity symbols such that a single inserted parity symbol does not violate the (1, 7) constraint in a run length limited code and furthermore the data following the insertion will not violate the (1, 10) constraint in a run length limited code. The state machines can be used as a trellis to perform maximum likelihood decoding on received coded data, thus performing soft algebraic error detection on received data. The invention thus guarantees better overall error rate performance than hard decision post processing of blocks of detected bits by a parity check matrix which is otherwise vulnerable to loss of bit synchronization at high linear density recording.
摘要翻译：用于代数校正来自磁阻或巨磁阻（MR / GMR）磁头回读波形的复数数字相位信号中的误差的系统和方法包括：数据状态机，其将相位符号编码为数据位，例如，（1,10）约束和产生奇偶校验符号的奇偶校验状态机，使得单个插入的奇偶校验符号不违反游程长度限制代码中的（1,7）约束，此外，插入之后的数据将不会违反（ 1，10）在运行长度限制代码中的约束。状态机可以用作网格，对接收到的编码数据进行最大似然解码，从而对接收到的数据执行软代数误差检测。因此，本发明保证比通过奇偶校验矩阵的硬判决后处理检测到的比特的更好的总体错误率性能，否则在高线性密度记录时易于丢失比特同步。

2. 发明授权

US06498692B1 System and method for processing MR/GMR head signal using phase measurement 有权
标题翻译：使用相位测量处理MR / GMR头信号的系统和方法
公开(公告)号：US06498692B1
公开(公告)日：2002-12-24
申请号：US09653746
申请日：2000-09-01
申请人： Martin Aureliano Hassner , Francesco Rezzi , Barry Marshall Trager
发明人： Martin Aureliano Hassner , Francesco Rezzi , Barry Marshall Trager
IPC分类号： G11B502
CPC分类号： G11B20/10046 , G11B5/02 , G11B5/035 , G11B5/09 , G11B20/10009 , G11B2005/0016
摘要： A circuit combines a read signal from an MR/GMR read head with a signal generated by a matched filter, the parameters of which depend on the geometry of the head and the output of which, generated every Nth clock period, includes a real part and an imaginary part that models an expected head response. The combined signal is phase equalized and sent to a complex correlator, which integrates the signal over N clock periods to output a correlated signal having real and imaginary portions of the Nth root of unity which correspond to bits in an N-clock data unit. The real and imaginary portions can subsequently be digitized and analyzed for errors.
摘要翻译：电路将来自MR / GMR读取头的读取信号与由匹配滤波器产生的信号相结合，其匹配滤波器的参数取决于头部的几何形状，并且其每第N个时钟周期产生的输出包括实际部分，模拟预期头部响应的虚构部分。组合信号被相位相等并发送到复相关器，该复相关器对N个时钟周期内的信号进行积分，以输出具有与第N个时钟数据单元中的位相对应的第N个单位根的实部和虚部的相关信号。实部和虚部可以随后被数字化并分析出错误。

3. 发明授权

US07595745B1 Circuit for converting a voltage range of a logic signal 有权
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07595745B1
公开(公告)日：2009-09-29
申请号：US11836619
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03M1/00
CPC分类号： H03K3/356113
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点将基于控制的第一状态时，开关选择性地将输出节点耦合到第一参考电压信号。具有电流源的源极跟随器电路建立第二参考电压。耦合到开关和源极跟随器电路并且具有逻辑门的逻辑电路在输出节点要从第一状态转变到第二状态时，根据控制信号将输出节点选择性地放电到第二参考电压州。

4. 发明授权

US07511649B1 Circuit for converting a voltage range of a logic signal 有权
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07511649B1
公开(公告)日：2009-03-31
申请号：US11846292
申请日：2007-08-28
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
IPC分类号： H03M1/66
CPC分类号： H03K17/6871 , H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal. The control signal indicates that the output node is to transition from the first state to the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态第二MOS晶体管具有耦合到输出节点的源极和耦合到偏置电压的栅极。当输出节点处于第二状态时，电流源电路选择性地偏压第二MOS晶体管，以充当源跟随器电路的一部分。另外，存储器电路具有耦合到输出节点的输入和输出。存储器电路被配置为当输出节点从第一状态转换到第二状态时临时存储输出节点的布尔值。此外，放电电路耦合到输出节点和第二参考电压。放电电路被配置为当输出节点从第一状态转变到第二状态时临时提供输出节点与第二参考电压之间的放电路径。放电电路具有耦合到存储器电路的输出的第一输入和耦合到控制信号的第二输入。控制信号表示输出节点要从第一状态转换到第二状态。

5. 发明授权

US6043943A Asymmetry correction for a read head 失效
标题翻译：读头的不对称校正
公开(公告)号：US6043943A
公开(公告)日：2000-03-28
申请号：US846782
申请日：1997-04-30
申请人： Francesco Rezzi , Giuseppe Patti
发明人： Francesco Rezzi , Giuseppe Patti
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B5/39 , G11B20/10
CPC分类号： G11B5/012 , G11B20/10009 , G11B5/09 , G11B2005/0016
摘要： A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.
摘要翻译：一种用于校正由磁阻头产生的响应信号中的不对称的方法和电路。磁阻头产生响应信号以传送从磁性介质存储装置读取的数字信息。通过平方输出信号，调制平方输出信号，以及从响应信号中减去经调制的平方输出信号以产生输出信号，以负反馈方式校正不对称性。该电路采用差分放大器作为输入级和吉尔伯特乘法器电路对输出信号进行平方。

6. 发明授权

US07629909B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07629909B1
公开(公告)日：2009-12-08
申请号：US11836628
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03M1/00
CPC分类号： H03K19/00361 , H03K17/162 , H03M1/742
摘要： In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.
摘要翻译：在转换控制信号的电压范围的电路中，当输出节点处于第一状态时，第一开关基于控制信号将输出节点选择性地耦合到第一参考电压。当输出节点处于第二状态时，第二开关基于控制信号选择性地建立第二参考电压，第二状态是第一状态的逻辑补码。反馈控制回路耦合到输出节点以响应于输出节点处的电压波动来维持第二参考电压。反馈控制回路包括电流镜和耦合到电流镜的晶体管。晶体管通过来自输出节点的反馈来控制，以修改由电流镜所建立的偏置电流，从而抵消电压波动。

7. 发明授权

US07609186B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07609186B1
公开(公告)日：2009-10-27
申请号：US11836584
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点处于第一状态时，第一晶体管选择性地将输出节点耦合到第一参考电压。当输出节点要从第一状态转变到第二状态时，第二晶体管通过电阻器选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。源跟随器电路具有耦合到输出节点并具有动态电流源的源极跟随器输出，动态电流源具有耦合到电阻器的控制输入。当输出节点处于第二状态时，第三晶体管选择性地将源极跟随器输出耦合到动态电流源。

8. 发明授权

US07605608B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07605608B1
公开(公告)日：2009-10-20
申请号：US11836571
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03M1/742
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态当输出节点从第一状态转变到第二状态时，第二MOS晶体管选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。具有电流源的源跟随器电路的输出耦合到输出节点。当输出节点处于第二状态时，第三MOS晶体管将源极跟随器电路的电流源选择性地耦合到第二参考电压。

9. 发明授权

US06492918B1 Code word having data bits and code bits and method for encoding data 有权
标题翻译：具有数据位和码位的码字和用于对数据进行编码的方法
公开(公告)号：US06492918B1
公开(公告)日：2002-12-10
申请号：US09410276
申请日：1999-09-30
申请人： Francesco Rezzi , Marcus Marrow
发明人： Francesco Rezzi , Marcus Marrow
IPC分类号： H03M506
CPC分类号： H03M13/098 , G11B20/14 , G11B20/18 , H03M13/09
摘要： A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.
摘要翻译：代码字包括第一组数据位，并且包括表示第二组数据位的代码位。代码字的一个实施例在其位之间具有最小的位转换概率。代码字的另一实施例包括奇偶校验位。与传统代码不同，包含这样的代码字的代码可以具有高效率和小错误传播。另外，通过包括更少的位转换，这种码字的序列导致更少的读取噪声，并且因此与已知码字的序列相比导致更少的读取错误。此外，与已知的错误检测技术相比，代码字可以包括奇偶校验位以允许改进的错误检测。因此，这样的代码字可以显着增加磁盘驱动器的有效写入和读取速度。

10. 发明授权

US07888973B1 Matrix time-to-digital conversion frequency synthesizer 有权
标题翻译：矩阵时 - 数转换频率合成器
公开(公告)号：US07888973B1
公开(公告)日：2011-02-15
申请号：US12133119
申请日：2008-06-04
申请人： Francesco Rezzi , Antonio Liscidini
发明人： Francesco Rezzi , Antonio Liscidini
IPC分类号： H03B21/00
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/197 , H03L2207/50
摘要： The present disclosure provides for a time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparators 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.
摘要翻译：本公开提供了一种时间到数字转换器（TDC）。数字转换器的时间可以包括参考入口，其接收参考信号并通过多个延迟元件传递参考信号;时钟信号入口，其接收时钟信号并使时钟信号通过另一组延迟元件，以及多个比较器，数量少于延迟元件总数。多个比较器1）接收延迟的参考和延迟时钟信号，以及2）输出一组比较结果，用于比较延迟参考对和延迟时钟信号对。

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