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1. 发明授权

US07511649B1 Circuit for converting a voltage range of a logic signal 有权
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07511649B1
公开(公告)日：2009-03-31
申请号：US11846292
申请日：2007-08-28
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
IPC分类号： H03M1/66
CPC分类号： H03K17/6871 , H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal. The control signal indicates that the output node is to transition from the first state to the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态第二MOS晶体管具有耦合到输出节点的源极和耦合到偏置电压的栅极。当输出节点处于第二状态时，电流源电路选择性地偏压第二MOS晶体管，以充当源跟随器电路的一部分。另外，存储器电路具有耦合到输出节点的输入和输出。存储器电路被配置为当输出节点从第一状态转换到第二状态时临时存储输出节点的布尔值。此外，放电电路耦合到输出节点和第二参考电压。放电电路被配置为当输出节点从第一状态转变到第二状态时临时提供输出节点与第二参考电压之间的放电路径。放电电路具有耦合到存储器电路的输出的第一输入和耦合到控制信号的第二输入。控制信号表示输出节点要从第一状态转换到第二状态。

2. 发明授权

US07705635B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07705635B1
公开(公告)日：2010-04-27
申请号：US11836635
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A source-follower circuit includes a current source and a source follower output, and the source follower output is coupled to the output node. A second MOS transistor selectively couples the source-follower circuit to a second reference voltage when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态源跟随器电路包括电流源和源极跟随器输出，并且源极跟随器输出耦合到输出节点。当输出节点处于第二状态时，第二MOS晶体管选择性地将源极跟随器电路耦合到第二参考电压。

3. 发明授权

US07629909B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07629909B1
公开(公告)日：2009-12-08
申请号：US11836628
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03M1/00
CPC分类号： H03K19/00361 , H03K17/162 , H03M1/742
摘要： In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.
摘要翻译：在转换控制信号的电压范围的电路中，当输出节点处于第一状态时，第一开关基于控制信号将输出节点选择性地耦合到第一参考电压。当输出节点处于第二状态时，第二开关基于控制信号选择性地建立第二参考电压，第二状态是第一状态的逻辑补码。反馈控制回路耦合到输出节点以响应于输出节点处的电压波动来维持第二参考电压。反馈控制回路包括电流镜和耦合到电流镜的晶体管。晶体管通过来自输出节点的反馈来控制，以修改由电流镜所建立的偏置电流，从而抵消电压波动。

4. 发明授权

US07609186B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07609186B1
公开(公告)日：2009-10-27
申请号：US11836584
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点处于第一状态时，第一晶体管选择性地将输出节点耦合到第一参考电压。当输出节点要从第一状态转变到第二状态时，第二晶体管通过电阻器选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。源跟随器电路具有耦合到输出节点并具有动态电流源的源极跟随器输出，动态电流源具有耦合到电阻器的控制输入。当输出节点处于第二状态时，第三晶体管选择性地将源极跟随器输出耦合到动态电流源。

5. 发明授权

US07605608B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07605608B1
公开(公告)日：2009-10-20
申请号：US11836571
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03M1/742
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态当输出节点从第一状态转变到第二状态时，第二MOS晶体管选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。具有电流源的源跟随器电路的输出耦合到输出节点。当输出节点处于第二状态时，第三MOS晶体管将源极跟随器电路的电流源选择性地耦合到第二参考电压。

6. 发明授权

US07595745B1 Circuit for converting a voltage range of a logic signal 有权
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07595745B1
公开(公告)日：2009-09-29
申请号：US11836619
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03M1/00
CPC分类号： H03K3/356113
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点将基于控制的第一状态时，开关选择性地将输出节点耦合到第一参考电压信号。具有电流源的源极跟随器电路建立第二参考电压。耦合到开关和源极跟随器电路并且具有逻辑门的逻辑电路在输出节点要从第一状态转变到第二状态时，根据控制信号将输出节点选择性地放电到第二参考电压州。

7. 发明授权

US08976163B2 Using clock detect circuitry to reduce panel turn-on time 有权
标题翻译：使用时钟检测电路减少面板开启时间
公开(公告)号：US08976163B2
公开(公告)日：2015-03-10
申请号：US13491430
申请日：2012-06-07
申请人： Daniel A. Villamizar , Ahmad Al-Dahle , Shafiq M. Jamal
发明人： Daniel A. Villamizar , Ahmad Al-Dahle , Shafiq M. Jamal
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G06F1/24 , G06F3/041
摘要： Systems, devices, and methods for using clock detector circuitry to reduce turn-on time of an electronic display, improve image quality, and reduce operations of a host are provided. In one example, a system may include a host configured to transmit a number of signals and a display driver coupled to the host. The number of signals may include a clock signal and data signals. The display driver is configured to drive a display based at least in part on the data signals. The display driver is also configured to be reset upon detection of the clock signal without waiting for a host-issued reset signal. A clock detect circuit configured to detect the clock signal may be configured to transmit an internal reset signal to reset the display driver without a dedicated host-issued reset signal.
摘要翻译：提供了使用时钟检测器电路来减少电子显示器的开启时间，提高图像质量和减少主机操作的系统，设备和方法。在一个示例中，系统可以包括被配置为发送多个信号的主机和耦合到主机的显示驱动器。信号的数量可以包括时钟信号和数据信号。显示驱动器被配置为至少部分地基于数据信号来驱动显示器。显示驱动器还被配置为在检测到时钟信号时被复位，而不等待主机发出的复位信号。被配置为检测时钟信号的时钟检测电路可以被配置为发送内部复位信号以复位显示驱动器，而不需要专用的主机发出的复位信号。

8. 发明授权

US08890545B2 Measurement of transistor gate source capacitance on a display system substrate using a replica transistor 有权
标题翻译：使用复制晶体管测量显示系统基板上的晶体管栅极源极电容
公开(公告)号：US08890545B2
公开(公告)日：2014-11-18
申请号：US13610729
申请日：2012-09-11
申请人： Shafiq M. Jamal , Hopil Bae , Sang Y Youn , Wei H. Yao
发明人： Shafiq M. Jamal , Hopil Bae , Sang Y Youn , Wei H. Yao
IPC分类号： G01R27/26
CPC分类号： G09G3/3648 , G09G3/006 , G09G3/3225 , G09G2320/02 , G09G2320/0209 , G09G2320/0693 , G09G2330/12 , G09G2380/02
摘要： Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A gate source capacitance of a constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be measured using a replica component that emulates the behavior of the component.
摘要翻译：可以提供具有诸如解复用器，栅极线和数据线驱动器之类的半导体微电子部件的显示系统和形成在显示器基板上的像素开关（例如构成有源矩阵显示面板的一部分的玻璃基板）的更好的性能。这些微电子部件之一的构成晶体管的栅极源极电容，例如作为特定显示元件的一部分的像素薄膜晶体管（TFT）可以使用模拟部件的行为的复制部件来测量。

9. 发明授权

US08803860B2 Gate driver fall time compensation 有权
标题翻译：门驱动器下降时间补偿
公开(公告)号：US08803860B2
公开(公告)日：2014-08-12
申请号：US13604580
申请日：2012-09-05
申请人： Shafiq M. Jamal
发明人： Shafiq M. Jamal
IPC分类号： G06F3/038
CPC分类号： G09G3/3648 , G09G2320/0219 , G09G2330/12
摘要： A display system includes a display panel of pixels, a gate driver and a compensation unit. The gate driver receives a control signal and based on the control signal, generates a gate signal to drive a transistor included in a pixel. The compensation unit measures and compensates for a fall time of the gate driver. The compensation unit includes a replica gate driver, a peak RMS detector, a comparator and a counter. The replica gate driver generates a replica gate signal based on the control signal. The peak RMS detector calculates a peak RMS of the replica gate signal. The comparator compares the peak RMS of the replica gate signal and a reference voltage and generates a comparator value. The counter is controlled by the comparator value to generate a compensation value used to adjust the gate driver and the replica gate driver. Other embodiments are also described and claimed.
摘要翻译：显示系统包括像素显示面板，栅极驱动器和补偿单元。栅极驱动器接收控制信号并且基于控制信号，产生栅极信号以驱动包括在像素中的晶体管。补偿单元测量和补偿门驱动器的下降时间。补偿单元包括复制栅极驱动器，峰值RMS检测器，比较器和计数器。复制栅极驱动器基于控制信号产生复制门信号。峰值RMS检测器计算复制门信号的峰值RMS。比较器比较复制门信号的峰值RMS和参考电压，并产生比较器值。计数器由比较器值控制，以产生用于调整栅极驱动器和复制栅极驱动器的补偿值。还描述和要求保护其他实施例。

10. 发明申请

US20130328851A1 GROUND NOISE PROPAGATION REDUCTION FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：用于电子设备的接地噪声传播减少
公开(公告)号：US20130328851A1
公开(公告)日：2013-12-12
申请号：US13599950
申请日：2012-08-30
申请人： Ahmad Al-Dahle , Shafiq M. Jamal
发明人： Ahmad Al-Dahle , Shafiq M. Jamal
IPC分类号： G09G5/00 , G05F3/02
CPC分类号： G09G3/3696 , G09G2300/0426 , G09G2330/028
摘要： A system and device for reducing ground bounce in circuitry. Utilization of a common ground supplied to multiple integrated circuits reduces the complexity and costs of producing circuitry but tends to interfere with signal quality within the circuitry by subjecting each integrated circuit to the ground bounce of every other integrated circuit. By introducing a source follower to selectively decouple and/or couple slave circuits within the circuitry, the ground bounce for the overall system can be reduced, thereby increasing the efficiency of interpreting signals within the circuitry.
摘要翻译：用于减少电路中接地反弹的系统和装置。利用提供给多个集成电路的公共场地降低了生成电路的复杂性和成本，但是通过使每个集成电路经受每个其他集成电路的地面反弹而趋向于干扰电路内的信号质量。通过引入源极跟随器来选择性地去耦合和/或耦合电路内的从属电路，可以减小整个系统的接地反弹，从而提高解释电路内的信号的效率。

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