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1. 发明授权

US5981364A Method of forming a silicon gate to produce silicon devices with improved performance 失效
标题翻译：形成硅栅极以产生具有改进性能的硅器件的方法
公开(公告)号：US5981364A
公开(公告)日：1999-11-09
申请号：US568195
申请日：1995-12-06
申请人： Mark T. Ramsbey , Hsingya Arthur Wang , Yu Sun
发明人： Mark T. Ramsbey , Hsingya Arthur Wang , Yu Sun
IPC分类号： H01L21/28 , H01L29/49
CPC分类号： H01L21/28035 , H01L29/4925
摘要： Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.
摘要翻译：本文公开了一种在硅器件的硅衬底上形成硅栅叠层的方法。形成硅栅极堆叠的方法包括以下步骤：在硅衬底上生长氧化物层，沉积薄层的硅以在氧化物层上形成薄的硅层，在薄层上沉积厚的硅层硅，并且将杂质引入仅硅的厚层中以形成硅栅极，由此硅栅极包括硅的薄层和具有杂质的厚的硅层。引入浓度的杂质，杂质浓度和厚层厚度在施加硅栅堆叠周围的保护性屏蔽氧化物层时阻碍氧化层侵入硅栅中。

2. 发明授权

US5747882A Device including means for preventing tungsten silicide lifting, and method of fabrication thereof 失效
标题翻译：包括防止硅化钨提升的装置的装置及其制造方法
公开(公告)号：US5747882A
公开(公告)日：1998-05-05
申请号：US744962
申请日：1996-11-07
申请人： Hsingya Arthur Wang , Mark T. Ramsbey , Yu Sun
发明人： Hsingya Arthur Wang , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L29/49 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/4933
摘要： In a semiconductor device, a layer of nitrogen doped polysilicon is applied to a gate oxide in turn provided on a semiconductor body, and then a silicide film is applied to the polysilicon layer. The nitrogen in the polysilicon layer inhibits growth of native oxide on the polysilicon layer prior to the application of silicide, and at subsequent high temperature processing steps, so that the problem of the silicide layer lifting from the polysilicon layer due to this native oxide growth is avoided during subsequent high temperature processing of the device.
摘要翻译：在半导体器件中，将氮掺杂多晶硅层依次设置在半导体本体上，然后将硅化物膜施加到多晶硅层。多晶硅层中的氮在施加硅化物之前抑制多晶硅层上的自然氧化物的生长，并且在随后的高温处理步骤中，使得由于该自然氧化物生长而导致从多晶硅层提升的硅化物层的问题是在设备的后续高温处理期间避免。

3. 发明授权

US5899726A Method of forming oxide isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成氧化物隔离的方法
公开(公告)号：US5899726A
公开(公告)日：1999-05-04
申请号：US891920
申请日：1997-07-14
申请人： Hsingya Arthur Wang , Mark T. Ramsbey , Jein-Chen Young
发明人： Hsingya Arthur Wang , Mark T. Ramsbey , Jein-Chen Young
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： After providing a patterned nitride layer over a patterned layer of oxide in turn disposed on a silicon substrate, a covering layer of oxide or polysilicon is deposited over the resulting structure to contact the substrate to hold the patterned nitride layer portions in position as field oxide is grown. In addition, field oxide growth rate slows at the edges of the nitride layer portions, allowing additional time for field oxide to flow as it is grown, relieving lifting force on the nitride layer portions, and providing an increase in silicon active area between field oxide regions.
摘要翻译：在依次设置在硅衬底上的图案化氧化物层上提供图案化氮化物层之后，在所得结构上沉积氧化物或多晶硅的覆盖层以接触衬底以将图案化的氮化物层部分保持在适当位置，因为场氧化物长大的。此外，场氧化物生长速率在氮化物层部分的边缘处减慢，允许场氧化物在其生长时流动的额外时间，减轻氮化物层部分上的提升力，并且提供场氧化物之间的硅有源面积的增加地区。

4. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

5. 发明授权

US06630384B1 Method of fabricating double densed core gates in sonos flash memory 有权
标题翻译：在sonos闪存中制造双激光核心门的方法
公开(公告)号：US06630384B1
公开(公告)日：2003-10-07
申请号：US09971483
申请日：2001-10-05
申请人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
发明人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
摘要翻译：本发明的一个方面涉及一种形成非易失性半导体存储器件的方法，包括在衬底上形成电荷俘获电介质，所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极，其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻，第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻，并且保形绝缘材料层位于每个相邻的存储单元栅极之间。

6. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

7. 发明授权

US06369416B1 Semiconductor device with contacts having a sloped profile 有权
标题翻译：具有倾斜轮廓的触头的半导体器件
公开(公告)号：US06369416B1
公开(公告)日：2002-04-09
申请号：US09404394
申请日：1999-09-23
申请人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
发明人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L2976
CPC分类号： H01L27/115 , H01L21/76804
摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.
摘要翻译：公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。触点具有限定倾斜轮廓的侧面。倾斜轮廓包括接触侧面和基体表面之间的角度小于大约八十八度。

8. 发明授权

US06342415B1 Method and system for providing reduced-sized contacts in a semiconductor device 失效
标题翻译：用于在半导体器件中提供减小尺寸的触点的方法和系统
公开(公告)号：US06342415B1
公开(公告)日：2002-01-29
申请号：US09404395
申请日：1999-09-23
申请人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
发明人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L218238
CPC分类号： H01L21/31144 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0.28 microns
摘要翻译：公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。所述至少一个接触件具有小于约0.28微米的减小的宽度

9. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

10. 发明授权

US06232630B1 Light floating gate doping to improve tunnel oxide reliability 有权
标题翻译：光浮栅掺杂提高隧道氧化可靠性
公开(公告)号：US06232630B1
公开(公告)日：2001-05-15
申请号：US09348583
申请日：1999-07-07
申请人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
发明人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
IPC分类号： H01L2972
CPC分类号： H01L29/42324
摘要： The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.
摘要翻译：隧道氧化物的可靠性通过浮栅的轻掺杂而改善，如同磷或砷原子一样。掺杂可以通过离子注入或原位沉积来实现。相对低的掺杂剂浓度进一步增强了浮栅上的电荷保持。

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