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    • 2. 发明申请
    • Method of forming floating gate array of flash memory device
    • 形成闪存器件的浮栅阵列的方法
    • US20070141785A1
    • 2007-06-21
    • US11641034
    • 2006-12-19
    • Jong Choi
    • Jong Choi
    • H01L21/336
    • H01L27/11521H01L27/115
    • The method of forming a floating gate array of a flash memory device includes: (a) sequentially forming a tunnel oxide film, a floating gate forming film, a capping oxide film and a first nitride film on a semiconductor substrate with an active device region defined by device isolation films; (b) patterning the first nitride film to form a first nitride film pattern; (c) forming first oxide film spacers on sidewalls of the first nitride film pattern; (d) selectively removing the first nitride film pattern; (e) forming a plurality of second nitride film patterns separated by the first oxide film spacers on the capping oxide film; (f) selectively removing the first oxide film spacers interposed between the plurality of second nitride film patterns and a portion of the capping oxide film to expose a surface of the floating gate forming film between the second nitride film patterns; (g) forming a plurality of floating gate patterns by removing a portion of the floating gate forming film exposed using the second nitride film patterns as an etching mask; and (h) oxidizing the sidewall of each of the plurality of floating gate patterns to form sidewall oxide films therebetween.
    • 形成闪速存储器件的浮置栅极阵列的方法包括:(a)在半导体衬底上依次形成隧道氧化膜,浮栅形成膜,封盖氧化物膜和第一氮化物膜,其中定义有源器件区域 通过器件隔离膜; (b)图案化所述第一氮化物膜以形成第一氮化物膜图案; (c)在第一氮化物膜图案的侧壁上形成第一氧化膜间隔物; (d)选择性地除去第一氮化物膜图案; (e)在所述封盖氧化膜上形成由所述第一氧化膜间隔物分离的多个第二氮化物膜图案; (f)选择性地去除夹在所述多个第二氮化物膜图案之间的所述第一氧化物膜间隔物和所述封盖氧化膜的一部分,以暴露所述第二氮化物膜图案之间的所述浮栅形成膜的表面; (g)通过去除使用第二氮化物膜图案暴露的浮栅形成膜的一部分作为蚀刻掩模来形成多个浮栅图案; 和(h)氧化多个浮栅图案中的每一个的侧壁以在其间形成侧壁氧化膜。
    • 3. 发明申请
    • Backlight unit
    • 背光单元
    • US20060221639A1
    • 2006-10-05
    • US11395163
    • 2006-04-03
    • Hoon JangJong Choi
    • Hoon JangJong Choi
    • F21V7/04
    • H01J65/046G02F1/133604G02F2001/133612G09G3/3406G09G2330/06H01J61/325
    • A backlight unit includes a case; a plurality of fluorescent lamps on the case, each fluorescent lamp having ends arranged in one direction, and having first and second electrodes provided at respective ends; a first power supply line connected with the first electrode; a second power supply line connected with the second electrode; a common electrode PCB arranged adjacent to the ends of the fluorescent lamps; a first common electrode on the common electrode PCB and connected with the first power supply line; a second common electrode on the common electrode PCB and connected with the second power supply line, the first and second common electrodes being spaced apart from each other; and an inverter to apply voltages to the first and second common electrodes.
    • 背光单元包括壳体; 在所述壳体上的多个荧光灯,每个荧光灯具有沿一个方向布置的端部,并且具有设置在各个端部的第一和第二电极; 与第一电极连接的第一电源线; 与第二电极连接的第二电源线; 布置成与荧光灯的端部相邻的公共电极PCB; 在公共电极PCB上的第一公共电极并与第一电源线连接; 在公共电极PCB上的与第二电源线连接的第二公共电极,第一和第二公共电极彼此间隔开; 以及向第一和第二公共电极施加电压的反相器。
    • 6. 发明申请
    • Method of scaling partial area of main picture
    • 缩放主画面部分区域的方法
    • US20050151885A1
    • 2005-07-14
    • US11005938
    • 2004-12-06
    • Jong Choi
    • Jong Choi
    • H04N7/01G06T3/40H04N5/44H04N5/45H04N9/74
    • H04N5/44G06T3/40H04N5/45H04N21/4316H04N21/440245H04N21/440263H04N21/4728
    • The present invention provides a method of scaling a partial area of a main picture, by which the partial area of the main picture can be magnified in a manner of scaling the partial area of the picture displayed on a screen like using a virtual magnifier without employing a separate expensive hardware resource. The present invention comprises a first step of making a main scaler extract image data of the partial area to be scaled from full image data according to prescribed scaling information including magnification/reduction information for the partial area of a display picture, a second step of making a sub-scaler scale the extracted image data of the partial area at a prescribed rate, and a third step of overlaying the scaled image data of the partial area on the full image data provided from the main scaler.
    • 本发明提供一种缩放主图像的部分区域的方法,通过该方法可以以不使用虚拟放大镜的方式缩放显示在屏幕上的图像的部分区域的方式放大主图像的部分区域 一个单独的昂贵的硬件资源。 本发明包括:第一步骤,使主缩放器根据包括用于显示图像的局部区域的放大/缩小信息的规定缩放信息,从全图像数据中提取部分区域的图像数据,第二步骤 以规定的速率对所提取的部分区域的图像数据进行分分割比例缩放;以及第三步骤,将部分区域的缩放图像数据重叠在从主缩放器提供的完整图像数据上。
    • 10. 发明申请
    • Digital signal processor having reconfigurable data paths
    • 具有可重构数据路径的数字信号处理器
    • US20060271610A1
    • 2006-11-30
    • US11192006
    • 2005-07-29
    • Seung LeeYong JeongJong Choi
    • Seung LeeYong JeongJong Choi
    • G06F15/00
    • G06F7/57
    • Disclosed herein is a Digital Signal Processor (DSP) having reconfigurable data paths necessary for processing for a specific use. The DSP includes a plurality of Arithmetic Logic Units (ALUs), pairs of input multiplexers, an output multiplexer, and a reconfiguration control unit. The plurality of ALUs performs unit operations. Each of the pairs of input multiplexers selects data, which will be input to a corresponding ALU, from among input data directed to operate by an instruction word, and output data of the ALUs. The output multiplexer selects one from among the output data of the ALUs, and outputs the selected output data. The reconfiguration control unit controls the data selections of the output multiplexer and the input multiplexers.
    • 这里公开了具有用于特定用途的处理所需的可重新配置数据路径的数字信号处理器(DSP)。 DSP包括多个算术逻辑单元(ALU),输入多路复用器对,输出多路复用器和重配置控制单元。 多个ALU执行单元操作。 输入多路复用器对中的每一对从选择指令字操作的输入数据和ALU的输出数据中选择将被输入到对应的ALU的数据。 输出多路复用器从ALU的输出数据中选择一个,并输出所选择的输出数据。 重新配置控制单元控制输出多路复用器和输入多路复用器的数据选择。