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1. 发明申请

US20080039488A1 Salt of naphthyridine carboxylic acid derivative 有权
标题翻译：萘啶羧酸衍生物的盐
公开(公告)号：US20080039488A1
公开(公告)日：2008-02-14
申请号：US11635069
申请日：2006-12-07
申请人： Ae Kim , Jin Lee , Ki Park , Jong Choi , Tae Lee , Jay Chang , Do Nam , Hoon Choi
发明人： Ae Kim , Jin Lee , Ki Park , Jong Choi , Tae Lee , Jay Chang , Do Nam , Hoon Choi
IPC分类号： A61K31/4375 , A61P11/16 , A61P13/02
CPC分类号： C07D471/04 , A61K31/4375 , C07B2200/13 , C07C309/04
摘要： 7-(3-Aminomethyl-4-methoxyiminopyrrolidin-1-yl)-1-cyclopropyl-6-fluoro-4-oxo-1,4-dihydro-1,8-naphthyridine-3-carboxylic acid methanesulfonate and hydrates thereof, processes for their preparation, pharmaceutical compositions comprising them, and their use in antibacterial therapy.
摘要翻译： 7-（3-氨基甲基-4-甲氧基亚氨基吡咯烷-1-基）-1-环丙基-6-氟-4-氧代-1,4-二氢-1,8-二氮杂萘-3-羧酸甲磺酸盐及其水合物，方法用于其制备，包含它们的药物组合物及其在抗菌治疗中的用途。

2. 发明申请

US20070069778A1 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US20070069778A1
公开(公告)日：2007-03-29
申请号：US11478094
申请日：2006-06-30
申请人： Hoon Choi , Jae-Jin Lee
发明人： Hoon Choi , Jae-Jin Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F7/68 , H03L7/0805
摘要： A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.
摘要翻译：具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。相位更新单元基于DLL源时钟信号执行相位更新操作，以输出DLL时钟信号。

3. 发明授权

US07605622B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07605622B2
公开(公告)日：2009-10-20
申请号：US11478094
申请日：2006-06-30
申请人： Hoon Choi , Jae-Jin Lee
发明人： Hoon Choi , Jae-Jin Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F7/68 , H03L7/0805
摘要： A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.
摘要翻译：具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。相位更新单元基于DLL源时钟信号执行相位更新操作，以输出DLL时钟信号。

4. 发明申请

US20170048499A9 TRANSMISSION AND DETECTION OF MULTI-CHANNEL SIGNALS IN REDUCED CHANNEL FORMAT 有权
标题翻译：传输和检测多通道信号在减少通道格式
公开(公告)号：US20170048499A9
公开(公告)日：2017-02-16
申请号：US14273400
申请日：2014-05-08
申请人： Hoon Choi , Daekyeung Kim , Wooseung Yang , Young Il Kim
发明人： Hoon Choi , Daekyeung Kim , Wooseung Yang , Young Il Kim
IPC分类号： H04N19/90 , H04N19/46
CPC分类号： H04N21/43635 , G09G5/006 , G09G2370/04 , G09G2370/12 , H04N5/38 , H04N5/4401 , H04N19/46 , H04N19/90
摘要： Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.
摘要翻译：本发明的实施例一般涉及以减小的信道格式传输和检测多信道信号。用于发送数据的方法的实施例包括确定是否要发送第一类型或第二类型的内容数据，其中第一类型的内容数据将以基本频率的第一倍发送，并且第二类型数据将以基本频率的第二倍发送。该方法还包括根据内容数据的类型从多个信道中选择一个或多个信道，根据所选择的信道中的内容数据的类型计算基频的第一或第二倍的频率，修改内容数据以适合单个输出通道，并且以所选择的基本频率的倍数通过单个输出通道发送修改的数据。

5. 发明授权

US09143507B2 Method, apparatus, and system for pre-authentication and processing of data streams 有权
标题翻译：用于预认证和处理数据流的方法，装置和系统
公开(公告)号：US09143507B2
公开(公告)日：2015-09-22
申请号：US12392000
申请日：2009-02-24
申请人： Hoon Choi , Gyudong Kim , Ook Kim , Alexander Peysakhovich , Michael Schumacher , Daeyun Shim
发明人： Hoon Choi , Gyudong Kim , Ook Kim , James D. Lyle , Alexander Peysakhovich , Michael Schumacher , Daeyun Shim
IPC分类号： H04L29/06
CPC分类号： H04L63/0876 , G09G5/006 , G09G2370/12 , G11B20/00086 , G11B20/00463 , H04N5/4401 , H04N5/913 , H04N7/1675 , H04N21/2541 , H04N21/4122 , H04N21/4367 , H04N21/4408 , H04N21/835
摘要： A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed.
摘要翻译：公开了一种用于预认证端口的方法，装置和系统。在一个实施例中，识别促进传输设备和接收设备之间的媒体内容通信的活动端口，而活动端口与第一高清内容保护（HDCP）引擎相关联。然后，识别处于空闲模式的非活动端口作为活动端口的备份端口，而非活动端口与第二HDCP引擎相关联。执行每个非活动端口的预认证，使得如果执行端口交换机，则经过认证的非活动端口可以随后替换活动端口。

6. 发明授权

US09131194B2 Display apparatus with a 3D synchronization signal transmitter disposed therein 有权
标题翻译：具有设置在其中的3D同步信号发送器的显示装置
公开(公告)号：US09131194B2
公开(公告)日：2015-09-08
申请号：US12973332
申请日：2010-12-20
申请人： Hoon Choi , Hyeon-Joo Lee
发明人： Hoon Choi , Hyeon-Joo Lee
IPC分类号： H04N5/64 , H04N13/04
CPC分类号： H04N5/64 , H04N13/341 , H04N13/398 , H04N2213/001 , H04N2213/008
摘要： A display apparatus in which a user can view a 3D image using shutter glasses is provided. The display apparatus, in which a user can view a three-dimensional (3D) image using shutter glasses, may include: a cover; a display module which is disposed in the cover and displays an image; and a transmitter which is disposed in the cover and transmits a synchronization signal to the shutter glasses to synchronize the image displayed by the display module with the shutter glasses.
摘要翻译：提供一种用户可以使用快门眼镜观看3D图像的显示装置。用户可以使用快门眼镜观看三维（3D）图像的显示装置可以包括：盖; 显示模块，其设置在所述盖中并显示图像; 以及发射机，其布置在所述盖中并将同步信号发送到快门眼镜，以使由显示模块显示的图像与快门眼镜同步。

7. 发明授权

US09001112B2 Display apparatus including a base unit having an image processing unit 有权
标题翻译：显示装置包括具有图像处理单元的基本单元
公开(公告)号：US09001112B2
公开(公告)日：2015-04-07
申请号：US13541230
申请日：2012-07-03
申请人： Hoon Choi , Hyeon-Joo Lee
发明人： Hoon Choi , Hyeon-Joo Lee
IPC分类号： G06F3/038 , H04N5/64 , G06F1/16 , G06Q50/18 , G06Q99/00 , F16M11/10
CPC分类号： H05K5/0017 , F16M11/10 , G06F1/1601 , G06F1/1605 , G06Q50/188 , G06Q99/00 , H04N5/64 , H05K5/0204 , H05K5/0234
摘要： Disclosed is a display apparatus with an improved structure of its display unit and main body. The display apparatus includes: a display unit which includes a display connector and displays an image; and a main body which includes a power supply unit for supplying power to the display unit, an image processing unit for outputting image signals, and a main body connector which is directly or indirectly connected to the display connector in order to supply the power and the image signals output from the power supply unit and the image processing unit, respectively, to the display unit.
摘要翻译：公开了一种显示装置，其显示单元和主体具有改进的结构。显示装置包括：显示单元，其包括显示连接器并显示图像; 以及主体，其包括用于向显示单元供电的电源单元，用于输出图像信号的图像处理单元和直接或间接连接到显示连接器的主体连接器，以便提供电力和图像信号分别从电源单元和图像处理单元输出到显示单元。

8. 发明授权

US08959378B2 Output timing control circuit and semiconductor apparatus using the same 有权
标题翻译：输出定时控制电路及使用其的半导体装置
公开(公告)号：US08959378B2
公开(公告)日：2015-02-17
申请号：US13219657
申请日：2011-08-27
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： G06F1/00 , H03K5/13
CPC分类号： H03K5/131
摘要： An output timing control circuit of a semiconductor apparatus includes a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock signal and output a first counting code, wherein the delay amount counter block is configured to control the delay amount of the output reset pulse signal depending upon a frequency of the external clock signal; an operation block configured to subtract a code value of the first counting code from a code value of a data output delay code, and output a delay control code; and a phase control block configured to control a phase of a read command signal by the number of clocks of a DLL clock signal corresponding to a code value of the delay control code, and output an output enable flag signal.
摘要翻译：半导体装置的输出定时控制电路包括：延迟量计数器块，被配置为基于外部时钟信号对输出复位脉冲信号的延迟量进行计数，并输出第一计数代码，其中延迟量计数器块被配置为控制输出复位脉冲信号的延迟量取决于外部时钟信号的频率; 操作块，被配置为从数据输出延迟码的代码值中减去第一计数代码的代码值，并输出延迟控制代码; 以及相位控制块，被配置为通过与延迟控制代码的代码值相对应的DLL时钟信号的时钟数来控制读取命令信号的相位，并输出输出使能标志信号。

9. 发明授权

US08947964B2 Current sense amplifiers, memory devices and methods 有权
标题翻译：电流检测放大器，存储器件和方法
公开(公告)号：US08947964B2
公开(公告)日：2015-02-03
申请号：US12820050
申请日：2010-06-21
申请人： Onegyun Na , Jongtae Kwak , Seong-Hoon Lee , Hoon Choi
发明人： Onegyun Na , Jongtae Kwak , Seong-Hoon Lee , Hoon Choi
IPC分类号： G11C7/02 , G11C7/06 , G11C11/4091
CPC分类号： G11C11/4091 , G11C7/02 , G11C7/06 , G11C7/062 , G11C7/065 , G11C11/4074 , G11C2207/063 , G11C2207/2281
摘要： A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.
摘要翻译：电流检测放大器可以包括耦合在放大器的差分输出节点之间的一个或多个钳位电路。钳位电路可以在读出放大器感测耦合到读出放大器的差分输入的存储器单元的状态的至少一部分期间被使能。在读出放大器以不同的时间以交错的方式感测存储器单元的状态的时间期间，钳位电路可能被禁用。钳位电路可能正在使电流检测放大器对噪声信号较不敏感。

10. 发明授权

US08643787B2 Mechanism for memory reduction in picture-in-picture video generation 有权
公开(公告)号：US08643787B2
公开(公告)日：2014-02-04
申请号：US12816437
申请日：2010-06-16
申请人： Daekyeung Kim , Wooseung Yang , Young Il Kim , Jeoong Sung Park , Hoon Choi
发明人： Daekyeung Kim , Wooseung Yang , Young Il Kim , Jeoong Sung Park , Hoon Choi
IPC分类号： H04N5/45
摘要： A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video.

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