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1. 发明授权

US06261933B1 Process for building borderless bitline, wordline amd DRAM structure 失效
标题翻译：构建无边界位线，字线amd DRAM结构的过程
公开(公告)号：US06261933B1
公开(公告)日：2001-07-17
申请号：US09494415
申请日：2000-01-31
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L213205
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，最小尺寸字线连接大致最小尺寸的单独栅极段，位线接触与字线无边界。本发明的另一个目的是提供具有单独的段栅极导体以及具有位线接触对该字线无边界的极小尺寸的栅极连接器。一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

2. 发明授权

US06420748B1 Borderless bitline and wordline DRAM structure 失效
标题翻译：无边界位线和字线DRAM结构
公开(公告)号：US06420748B1
公开(公告)日：2002-07-16
申请号：US09657968
申请日：2000-09-08
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，最小尺寸字线连接大致最小尺寸的单独栅极段，位线接触与字线无边界。本发明的另一个目的是提供具有单独的段栅极导体以及具有位线接触对该字线无边界的极小尺寸的栅极连接器。一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

3. 发明授权

US06175128B1 Process for building borderless bitline, wordline and DRAM structure and resulting structure 失效
标题翻译：构建无边界位线，字线和DRAM结构以及结构的过程
公开(公告)号：US06175128B1
公开(公告)日：2001-01-16
申请号：US09052538
申请日：1998-03-31
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the worldline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，极小维度字线将大致最小维度单独的门段链接到位线接触与世界线无边界。本发明的另一个目的是提供一种具有单独的段栅极导体和一个极小尺寸的栅极连接器的晶体管，其中位线接触与字线无边界。一种半导体结构及其制造方法，包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

4. 发明授权

US06271555B1 Borderless wordline for DRAM cell 失效
标题翻译： DRAM单元的无边界字线
公开(公告)号：US06271555B1
公开(公告)日：2001-08-07
申请号：US09052403
申请日：1998-03-31
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/10891 , Y10S257/905 , Y10S257/907 , Y10S257/908
摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.
摘要翻译：公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还具有具有源/漏区的单晶半导体衬底。主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

5. 发明授权

US6121128A Method for making borderless wordline for DRAM cell 失效
标题翻译：为DRAM单元制作无边界字线的方法
公开(公告)号：US6121128A
公开(公告)日：2000-09-19
申请号：US398659
申请日：1999-09-17
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
IPC分类号： H01L21/8242 , H01L21/4763
CPC分类号： H01L27/10873 , H01L27/10891 , Y10S257/905 , Y10S257/907 , Y10S257/908
摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.
摘要翻译：公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还具有具有源/漏区的单晶半导体衬底。主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

6. 发明授权

US06225165B1 High density SRAM cell with latched vertical transistors 失效
标题翻译：具有锁存垂直晶体管的高密度SRAM单元
公开(公告)号：US06225165B1
公开(公告)日：2001-05-01
申请号：US09076728
申请日：1998-05-13
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： H01L21336
CPC分类号： G11C11/39 , G11C11/41 , H01L27/11 , H01L27/1104
摘要： High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
摘要翻译：高密度静态存储单元和阵列，其包含门控侧向双极晶体管，可以锁定在双稳态导通状态。每个晶体管存储单元包括在写入操作期间脉冲偏置以锁存单元的两个栅极。还提供了一种用于创建电池和阵列的CMOS制造工艺。

7. 发明授权

US6128216A High density planar SRAM cell with merged transistors 失效
标题翻译：具有合并晶体管的高密度平面SRAM单元
公开(公告)号：US6128216A
公开(公告)日：2000-10-03
申请号：US76766
申请日：1998-05-13
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： G11C11/39 , G11C11/411 , H01L21/8244 , H01L27/11 , G11C11/00 , G11C11/36
CPC分类号： H01L27/11 , G11C11/39 , G11C11/411
摘要： Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
摘要翻译：区域有效的静态存储单元和包含p-n-p-n或n-p-n-p晶体管的阵列，其可以在双稳态导通状态下被锁存。每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的门。还提供了其中晶体管共享公共区域的链接存储器单元。

8. 发明授权

US06773968B1 High density planar SRAM cell using bipolar latch-up and gated diode breakdown 失效
标题翻译：高密度平面SRAM单元采用双极锁存和门控二极管击穿
公开(公告)号：US06773968B1
公开(公告)日：2004-08-10
申请号：US09609813
申请日：2000-07-03
申请人： Leonard Forbes , Wendell P. Noble, Jr.
发明人： Leonard Forbes , Wendell P. Noble, Jr.
IPC分类号： H01L21332
CPC分类号： H01L27/1203 , H01L27/1027 , Y10S257/903
摘要： Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
摘要翻译：区域有效的静态存储单元和包含p-n-p-n或n-p-n-p晶体管的阵列，其可以在双稳态导通状态下被锁存。每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的栅极。还提供了其中晶体管共享公共区域的链接存储器单元。

9. 发明授权

US6022781A Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack 失效
标题翻译：用于制造具有与门堆叠自对准的凸起STI隔离的MOSFET的方法
公开(公告)号：US6022781A
公开(公告)日：2000-02-08
申请号：US772708
申请日：1996-12-23
申请人： Wendell P. Noble, Jr. , Ashwin K. Ghatalia , Badih El-Kareh
发明人： Wendell P. Noble, Jr. , Ashwin K. Ghatalia , Badih El-Kareh
IPC分类号： H01L21/8242 , H01L21/08 , H01L29/00 , H01L29/76
CPC分类号： H01L27/10861
摘要： A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
摘要翻译：一种半导体结构，包括具有栅极导体的晶体管，栅极导体具有由凸起的隔离结构（例如STI）限定的第一和第二边缘。源极扩散与第三边缘自对准，漏极扩散与栅电极的第四边缘自对准。

10. 发明授权

US5512767A Trench capacitor field shield with sidewall contact 失效
标题翻译：沟槽电容器屏蔽层与侧壁接触
公开(公告)号：US5512767A
公开(公告)日：1996-04-30
申请号：US355942
申请日：1994-12-13
申请人： Wendell P. Noble, Jr.
发明人： Wendell P. Noble, Jr.
IPC分类号： H01L27/108 , H01L23/58
CPC分类号： H01L27/10829
摘要： Structures and methods are presented for forming a field shield for a trench capacitor for a memory cell with a contact through insulator along a sidewall of the trench to a desired region of the semiconducting substrate. The desired region is typically held at a substantially fixed potential; in any case it does not include a node diffusion.
摘要翻译：呈现了用于形成用于存储单元的沟槽电容器的场屏蔽的结构和方法，所述存储器单元具有沿沟槽的侧壁的接触绝缘体到半导体衬底的期望区域。期望的区域通常保持在基本上固定的电位; 在任何情况下，它不包括节点扩散。

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