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1. 发明授权

US06225165B1 High density SRAM cell with latched vertical transistors 失效
标题翻译：具有锁存垂直晶体管的高密度SRAM单元
公开(公告)号：US06225165B1
公开(公告)日：2001-05-01
申请号：US09076728
申请日：1998-05-13
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： H01L21336
CPC分类号： G11C11/39 , G11C11/41 , H01L27/11 , H01L27/1104
摘要： High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
摘要翻译：高密度静态存储单元和阵列，其包含门控侧向双极晶体管，可以锁定在双稳态导通状态。每个晶体管存储单元包括在写入操作期间脉冲偏置以锁存单元的两个栅极。还提供了一种用于创建电池和阵列的CMOS制造工艺。

2. 发明授权

US6128216A High density planar SRAM cell with merged transistors 失效
标题翻译：具有合并晶体管的高密度平面SRAM单元
公开(公告)号：US6128216A
公开(公告)日：2000-10-03
申请号：US76766
申请日：1998-05-13
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： G11C11/39 , G11C11/411 , H01L21/8244 , H01L27/11 , G11C11/00 , G11C11/36
CPC分类号： H01L27/11 , G11C11/39 , G11C11/411
摘要： Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
摘要翻译：区域有效的静态存储单元和包含p-n-p-n或n-p-n-p晶体管的阵列，其可以在双稳态导通状态下被锁存。每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的门。还提供了其中晶体管共享公共区域的链接存储器单元。

3. 发明授权

US06773968B1 High density planar SRAM cell using bipolar latch-up and gated diode breakdown 失效
标题翻译：高密度平面SRAM单元采用双极锁存和门控二极管击穿
公开(公告)号：US06773968B1
公开(公告)日：2004-08-10
申请号：US09609813
申请日：2000-07-03
申请人： Leonard Forbes , Wendell P. Noble, Jr.
发明人： Leonard Forbes , Wendell P. Noble, Jr.
IPC分类号： H01L21332
CPC分类号： H01L27/1203 , H01L27/1027 , Y10S257/903
摘要： Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
摘要翻译：区域有效的静态存储单元和包含p-n-p-n或n-p-n-p晶体管的阵列，其可以在双稳态导通状态下被锁存。每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的栅极。还提供了其中晶体管共享公共区域的链接存储器单元。

4. 发明授权

US06936886B2 High density SRAM cell with latched vertical transistors 失效
标题翻译：具有锁存垂直晶体管的高密度SRAM单元
公开(公告)号：US06936886B2
公开(公告)日：2005-08-30
申请号：US09750111
申请日：2000-12-29
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： G11C11/41 , H01L27/11 , H01L29/76 , H01L29/788
CPC分类号： G11C11/39 , G11C11/41 , H01L27/11 , H01L27/1104
摘要： High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
摘要翻译：高密度静态存储单元和阵列，其包含门控侧向双极晶体管，可以锁定在双稳态导通状态。每个晶体管存储单元包括在写入操作期间脉冲偏置以锁存单元的两个栅极。还提供了一种用于创建电池和阵列的CMOS制造工艺。

5. 发明授权

US6104045A High density planar SRAM cell using bipolar latch-up and gated diode breakdown 失效
标题翻译：高密度平面SRAM单元采用双极锁存和门控二极管击穿
公开(公告)号：US6104045A
公开(公告)日：2000-08-15
申请号：US076745
申请日：1998-05-13
申请人： Leonard Forbes , Wendell P. Noble, Jr.
发明人： Leonard Forbes , Wendell P. Noble, Jr.
IPC分类号： H01L27/102 , H01L27/12 , H01L29/74 , H01L27/11
CPC分类号： H01L27/1203 , H01L27/1027 , Y10S257/903
摘要： Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
摘要翻译：区域有效的静态存储单元和包含p-n-p-n或n-p-n-p晶体管的阵列，其可以在双稳态导通状态下被锁存。每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的栅极。还提供了其中晶体管共享公共区域的链接存储器单元。

6. 发明授权

US07105386B2 High density SRAM cell with latched vertical transistors 有权
公开(公告)号：US07105386B2
公开(公告)日：2006-09-12
申请号：US10795516
申请日：2004-03-09
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： H01L21/332 , H01L21/8238 , H01L21/8234
CPC分类号： G11C11/39 , G11C11/41 , H01L27/11 , H01L27/1104
摘要： High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

7. 发明授权

US06964903B2 Method of fabricating a transistor on a substrate to operate as a fully depleted structure 失效
标题翻译：在基板上制造晶体管以作为完全耗尽的结构工作的方法
公开(公告)号：US06964903B2
公开(公告)日：2005-11-15
申请号：US10057225
申请日：2002-01-25
申请人： Leonard Forbes , Wendell P. Noble, Jr.
发明人： Leonard Forbes , Wendell P. Noble, Jr.
IPC分类号： H01L27/07 , H01L29/78 , H03D7/12 , H01L21/336
CPC分类号： H01L29/7831 , H01L27/0705 , H03D7/125
摘要： A method provides a structure that includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The method includes forming a body region of the dual-gated MOSFET as a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.
摘要翻译：一种方法提供了包括双栅极金属氧化物半导体场效应晶体管（MOSFET）的结构。双门控MOSFET可以根据当前的CMOS处理技术制造。该方法包括将双门控MOSFET的体区形成为完全耗尽的结构。该结构包括位于身体区域的相对侧的相对侧上的两个门。此外，该结构作为一个器件工作，其中一个栅极的阈值电压取决于另一个栅极的偏置。因此，该结构在模拟电路应用中产生取决于施加到门的信号的乘积的小信号分量，而不是简单地取决于两个信号之和的结构。

8. 发明授权

US06545297B1 High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown 失效
标题翻译：使用门控二极管击穿引起的双极性闭锁的高密度垂直SRAM单元
公开(公告)号：US06545297B1
公开(公告)日：2003-04-08
申请号：US09076487
申请日：1998-05-13
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： H01L2974
CPC分类号： H01L29/87 , G11C11/4113
摘要： Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
摘要翻译：区域有效的静态存储单元和包含可以锁定在双稳态导通状态的p-n-p-n晶体管的阵列。每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的栅极。还提供了一种用于创建电池和阵列的CMOS制造工艺。

9. 发明授权

US06503790B2 High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown 失效
公开(公告)号：US06503790B2
公开(公告)日：2003-01-07
申请号：US09871682
申请日：2001-06-04
申请人： Wendell P. Noble, Jr. , Leonard Forbes
发明人： Wendell P. Noble, Jr. , Leonard Forbes
IPC分类号： H01L218244
CPC分类号： H01L29/87 , G11C11/4113
摘要： Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

10. 发明授权

US6121128A Method for making borderless wordline for DRAM cell 失效
标题翻译：为DRAM单元制作无边界字线的方法
公开(公告)号：US6121128A
公开(公告)日：2000-09-19
申请号：US398659
申请日：1999-09-17
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
IPC分类号： H01L21/8242 , H01L21/4763
CPC分类号： H01L27/10873 , H01L27/10891 , Y10S257/905 , Y10S257/907 , Y10S257/908
摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.
摘要翻译：公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还具有具有源/漏区的单晶半导体衬底。主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

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