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1. 发明授权

US07035998B1 Clustering stream and/or instruction queues for multi-streaming processors 有权
标题翻译：用于多流处理器的聚集流和/或指令队列
公开(公告)号：US07035998B1
公开(公告)日：2006-04-25
申请号：US09706157
申请日：2000-11-03
申请人： Mario Nemirovsky , Stephen W. Melvin , Nandakumar Sampath , Enrique Musoll , Hector Urdaneta
发明人： Mario Nemirovsky , Stephen W. Melvin , Nandakumar Sampath , Enrique Musoll , Hector Urdaneta
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3891
摘要： A pipelined multistreaming processor has an instruction source, a first cluster of a plurality of streams fetching instructions from the instruction source, a second cluster of a plurality of streams fetching instructions from the instruction source, dedicated instruction queues for individual streams in each cluster, a first dedicated dispatch stage in the first cluster for dispatching instructions to execution units, and a second dedicated dispatch stage in the second cluster for selecting and dispatching instructions to execution units. The processor is characterized in that the clusters operate independently, with the dedicated dispatch stage taking instructions only from the instruction queues in the individual clusters to which the dispatch stages are dedicated. In preferred embodiments there are dedicated fetch and dispatch stages for streams in the clusters, and dedicated execution units to which instructions may be dispatched.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流的第一簇，从指令源获取指令的多个流的第二簇，每个簇中的各个流的专用指令队列，用于向执行单元发送指令的第一集群中的第一专用调度阶段，以及用于向执行单元选择和分派指令的第二集群中的第二专用调度阶段。处理器的特征在于，集群独立地操作，专用调度阶段仅从调度阶段专用的各个集群中的指令队列获取指令。在优选实施例中，存在用于集群中的流的专用获取和分派阶段以及可以向其发送指令的专用执行单元。

2. 发明授权

US07280548B2 Method and apparatus for non-speculative pre-fetch operation in data packet processing 有权
标题翻译：数据包处理中非推测性预取操作的方法和装置
公开(公告)号：US07280548B2
公开(公告)日：2007-10-09
申请号：US11278890
申请日：2006-04-06
申请人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
摘要翻译：提供了一种系统，用于使得能够在分组处理器的即时分组处理之前的后台执行用于处理指令的非推测性预取操作。该系统包括用于接收数据分组并将其排入待处理的分组管理单元，用于处理数据分组的处理器单元，用于保存上下文寄存器的处理器核心存储器和用于处理的功能单元，用于保存多个指令线程的存储器以及用于将队列与指向开始指令线程的指针相关联的软件可配置硬件表。分组管理单元在处理器核心中选择用于处理数据分组的可用上下文，参考表格，并将指针传送到处理器，使得处理器能够对指令进行非推测性预取。

3. 发明申请

US20060215670A1 METHOD AND APPARATUS FOR NON-SPECULATIVE PRE-FETCH OPERATION IN DATA PACKET PROCESSING 有权
标题翻译：数据分组处理中非调制型预充电操作的方法和装置
公开(公告)号：US20060215670A1
公开(公告)日：2006-09-28
申请号：US11278890
申请日：2006-04-06
申请人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
摘要翻译：提供了一种系统，用于使得能够在分组处理器的即时分组处理之前的后台执行用于处理指令的非推测性预取操作。该系统包括用于接收数据分组并将其排入待处理的分组管理单元，用于处理数据分组的处理器单元，用于保存上下文寄存器的处理器核心存储器和用于处理的功能单元，用于保存多个指令线程的存储器以及用于将队列与指向开始指令线程的指针相关联的软件可配置硬件表。分组管理单元在处理器核心中选择用于处理数据分组的可用上下文，参考表格，并将指针传送到处理器，使得处理器能够对指令进行非推测性预取。

4. 发明授权

US07042887B2 Method and apparatus for non-speculative pre-fetch operation in data packet processing 有权
公开(公告)号：US07042887B2
公开(公告)日：2006-05-09
申请号：US09900393
申请日：2001-07-05
申请人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.

5. 发明授权

US08081645B2 Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment 有权
标题翻译：分组处理环境中的流处理单元（SPU）和分组管理单元（PMU）之间的上下文共享
公开(公告)号：US08081645B2
公开(公告)日：2011-12-20
申请号：US12649132
申请日：2009-12-29
申请人： Enrique Musoll , Mario Nemirovsky
发明人： Enrique Musoll , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/12 , H04L69/22
摘要： A method for processing multiple data packets includes receiving from a network interface, at a packet management unit (PMU), a data packet for processing, and determining whether to store or drop the data packet. The method further includes queueing the data packet in a queue within a queueing system and preloading a portion of the data packet into a context from a pool of contexts in a stream processing unit (SPU). The queued data packet referenced by the context is processed by the SPU and outputted to the network interface.
摘要翻译：一种用于处理多个数据分组的方法，包括从分组管理单元（PMU）的网络接口接收用于处理的数据分组，以及确定是否存储或丢弃数据分组。该方法还包括将数据分组排队在排队系统内的队列中，并将数据分组的一部分从流处理单元（SPU）中的上下文池预加载到上下文中。由上下文引用的排队数据包由SPU处理并输出到网络接口。

6. 发明申请

US20080270757A1 Fetch and Dispatch Disassociation Apparatus for Multistreaming Processors 有权
标题翻译：用于多数据流处理器的获取和调度关联装置
公开(公告)号：US20080270757A1
公开(公告)日：2008-10-30
申请号：US12173560
申请日：2008-07-15
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.
摘要翻译：动态多流处理器具有指令队列，对应于指令流的每个指令队列和执行单元。动态多流处理器还具有调度阶段，用于从一个指令队列中选择至少一个指令，并将所选择的至少一个指令发送到执行单元之一。最后，动态多流处理器具有与每个指令队列相关联的用于指示每个队列中的指令数量的队列计数器，以及与每个指令队列相关联的提取计数器，用于指示当相关联的指令时从其获得指令的地址队列不满。动态多数据流处理器还可以具有用于指示下一个指令地址的读取计数器，当相关联的指令队列未满时，该指令地址从其获得至少一个指令。动态多流处理器还可以具有用于指示下一个指令地址的第二计数器。

7. 发明授权

US07165257B2 Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts 有权
标题翻译：用于激活处理器核心中的一组非活动上下文中的一个用于服务中断的上下文选择和激活机制
公开(公告)号：US07165257B2
公开(公告)日：2007-01-16
申请号：US09927129
申请日：2001-08-10
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F9/46 , G06F3/00 , G06F9/00
CPC分类号： G06F9/461 , G06F9/4812 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.
摘要翻译：提供数据分组处理器中的逻辑系统用于选择和释放多个上下文中的一个。所选择和发布的上下文专用于使得能够处理对应于在数据分组处理中生成的中断并且待服务的中断服务例程。该系统包括用于确定所有上下文的控制状态的第一确定逻辑，用于确定上下文是否空闲的第二确定逻辑，用于选择上下文的选择逻辑和用于释放所选择的上下文的上下文释放机制。由逻辑系统确定所有上下文由不对分组处理负责的实体单独拥有，并且至少一个上下文是空闲的，触发所述至少一个空闲上下文中空闲的一个空闲上下文到负责的实体用于数据包处理。

8. 发明授权

US07058065B2 Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing 有权
公开(公告)号：US07058065B2
公开(公告)日：2006-06-06
申请号：US09924755
申请日：2001-08-07
申请人： Enrique Musoll , Thomas Y. Yeh , Mario Nemirovsky
发明人： Enrique Musoll , Thomas Y. Yeh , Mario Nemirovsky
IPC分类号： H04L12/56 , G06F13/00
CPC分类号： G06F9/546 , H04L49/201 , H04L49/205 , H04L49/901 , H04L49/9073
摘要： A logic system for resolving port contentions associated with memory-access requests in data packet routing is provided. The logic system comprises a determination logic for assessing and reporting port status of busy or not busy, a command mechanism for issuing commands contingent on determination results and a staged buffer memory for holding pending requests waiting for permission to access the memory. A single request at the head of the buffer memory is considered for port access whereupon if a port is determined to be busy, the command logic issues appropriate commands to units responsible for downloading packets from the memory and for sending new memory-access requests.

9. 发明申请

US20100103938A1 Context Sharing Between A Streaming Processing Unit (SPU) and A Packet Management Unit (PMU) In A Packet Processing Environment 有权
标题翻译：在分组处理环境中的流处理单元（SPU）和分组管理单元（PMU）之间的上下文共享
公开(公告)号：US20100103938A1
公开(公告)日：2010-04-29
申请号：US12649132
申请日：2009-12-29
申请人： Enrique MUSOLL , Mario Nemirovsky
发明人： Enrique MUSOLL , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/12 , H04L69/22
摘要： A context-selection mechanism is provided for selecting a best context from a pool of contexts for processing a data packet. The context selection mechanism comprises, an interface for communicating with a multi-streaming processor; circuitry for computing input data into a result value according to logic rule and for selecting a context based on the computed value and a loading mechanism for preloading the packet information into the selected context for subsequent processing. The computation of the input data functions to enable identification and selection of a best context for processing a data packet according to the logic rule at the instant time such that a multitude of subsequent context selections over a period of time acts to balance load pressure on functional units housed within the multi-streaming processor and required for packet processing. In preferred aspects, programmable singular or multiple predictive rules of logic are utilized in the selection process.
摘要翻译：提供了一种上下文选择机制，用于从用于处理数据分组的上下文池中选择最佳上下文。上下文选择机制包括：用于与多流处理器通信的接口; 用于根据逻辑规则将输入数据计算到结果值中并基于所计算的值来选择上下文的电路，以及用于将分组信息预加载到所选择的上下文中用于后续处理的加载机制。输入数据的计算功能用于根据逻辑规则来识别和选择用于处理数据分组的最佳上下文，使得在一段时间内多个随后的上下文选择用于平衡负载压力对功能性单元被容纳在多流处理器内并且需要进行数据包处理。在优选方面，在选择过程中利用可编程单数或多重预测逻辑规则。

10. 发明授权

US07197043B2 Method for allocating memory space for limited packet head and/or tail growth 有权
标题翻译：用于为有限的包头和/或尾部增长分配存储器空间的方法
公开(公告)号：US07197043B2
公开(公告)日：2007-03-27
申请号：US11278901
申请日：2006-04-06
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： H04J3/26
CPC分类号： H04L49/9073 , H04L49/90 , H04L49/901 , H04L49/9026 , H04L49/9047
摘要： A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
摘要翻译：提供了一种硬件/软件系统，用于以围绕要存储在存储器中的数据分组的缓冲区的形式分配存储器。硬件/软件系统包括：第一和第二寄存器，用于存储表示在一个寄存器中的单独的值，在要存储的数据分组的第一行之前的存储器的量，另一个存储在数据包的最后一行的量存储用于根据使用寄存器值计算的计算结果和要存储的数据分组的大小分配存储器的硬件机制，以及用于处理存储的数据分组并用于将任何新的增长数据写入到指定的缓冲区中的软件数据包。

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