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1. 发明申请

US20070260852A1 FETCH AND DISPATCH DISASSOCIATION APPARATUS FOR MULTI-STREAMING PROCESSORS 有权
标题翻译：多流程处理器的FETCH和DISPATCH分配设备
公开(公告)号：US20070260852A1
公开(公告)日：2007-11-08
申请号：US11539322
申请日：2006-10-06
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enrique Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

2. 发明申请

US20080270757A1 Fetch and Dispatch Disassociation Apparatus for Multistreaming Processors 有权
标题翻译：用于多数据流处理器的获取和调度关联装置
公开(公告)号：US20080270757A1
公开(公告)日：2008-10-30
申请号：US12173560
申请日：2008-07-15
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.
摘要翻译：动态多流处理器具有指令队列，对应于指令流的每个指令队列和执行单元。动态多流处理器还具有调度阶段，用于从一个指令队列中选择至少一个指令，并将所选择的至少一个指令发送到执行单元之一。最后，动态多流处理器具有与每个指令队列相关联的用于指示每个队列中的指令数量的队列计数器，以及与每个指令队列相关联的提取计数器，用于指示当相关联的指令时从其获得指令的地址队列不满。动态多数据流处理器还可以具有用于指示下一个指令地址的读取计数器，当相关联的指令队列未满时，该指令地址从其获得至少一个指令。动态多流处理器还可以具有用于指示下一个指令地址的第二计数器。

3. 发明授权

US07139898B1 Fetch and dispatch disassociation apparatus for multistreaming processors 有权
标题翻译：用于多数据流处理器的获取和调度分离装置
公开(公告)号：US07139898B1
公开(公告)日：2006-11-21
申请号：US09706154
申请日：2000-11-03
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/312
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

4. 发明授权

US07406586B2 Fetch and dispatch disassociation apparatus for multi-streaming processors 有权
标题翻译：用于多流处理器的获取和调度分离装置
公开(公告)号：US07406586B2
公开(公告)日：2008-07-29
申请号：US11539322
申请日：2006-10-06
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

5. 发明申请

US20090187739A1 Method and Apparatus for Improved Computer Load and Store Operations 审中-公开
标题翻译：用于改进计算机负载和存储操作的方法和装置
公开(公告)号：US20090187739A1
公开(公告)日：2009-07-23
申请号：US12411913
申请日：2009-03-26
申请人： Mario NEMIROVSKY , Enrique Musoll , Narendra Sankar , Stephen Melvin
发明人： Mario NEMIROVSKY , Enrique Musoll , Narendra Sankar , Stephen Melvin
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
摘要翻译：扩展了计算机系统中的加载和存储操作，以提供流加载和存储和掩蔽加载和存储。在Stream操作中，CPU执行Stream指令，该指令通过适当的参数指示存储器中的第一个地址或寄存器文件中的第一个寄存器，从开始读取数据实体，以及第一个地址或寄存器，从开始存储实体和一些要读写的实体。在屏蔽加载和屏蔽存储操作中，存储的掩码用于指示相对于第一个地址和寄存器进行加载和存储的模式。针对掩码教授了位线矢量方法。

6. 发明申请

US20080040577A1 METHOD AND APPARATUS FOR IMPROVED COMPUTER LOAD AND STORE OPERATIONS 有权
标题翻译：改进计算机负载和存储操作的方法和装置
公开(公告)号：US20080040577A1
公开(公告)日：2008-02-14
申请号：US11876442
申请日：2007-10-22
申请人： Mario Nemirovsky , Enrique Musoll , Narendra Sankar , Stephen Melvin
发明人： Mario Nemirovsky , Enrique Musoll , Narendra Sankar , Stephen Melvin
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
摘要翻译：扩展了计算机系统中的加载和存储操作，以提供流加载和存储和掩蔽加载和存储。在Stream操作中，CPU执行Stream指令，该指令通过适当的参数指示存储器中的第一地址或寄存器文件中的第一个寄存器，从开始读取数据实体，以及从开始存储实体的第一地址或寄存器，以及一些要读写的实体。在屏蔽加载和屏蔽存储操作中，存储的掩码用于指示相对于第一个地址和寄存器进行加载和存储的模式。针对掩码教授了位线矢量方法。

7. 发明授权

US07529907B2 Method and apparatus for improved computer load and store operations 有权
标题翻译：用于改进计算机负载和存储操作的方法和装置
公开(公告)号：US07529907B2
公开(公告)日：2009-05-05
申请号：US11876442
申请日：2007-10-22
申请人： Mario D. Nemirovsky , Stephen Melvin , Enrique Musoll , Narendra Sankar
发明人： Mario D. Nemirovsky , Stephen Melvin , Enrique Musoll , Narendra Sankar
IPC分类号： G06F9/312 , G06F9/305
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
摘要翻译：扩展了计算机系统中的加载和存储操作，以提供流加载和存储和掩蔽加载和存储。在Stream操作中，CPU执行Stream指令，该指令通过适当的参数指示存储器中的第一地址或寄存器文件中的第一个寄存器，从开始读取数据实体，以及从开始存储实体的第一地址或寄存器，以及一些要读写的实体。在屏蔽加载和屏蔽存储操作中，存储的掩码用于指示相对于第一个地址和寄存器进行加载和存储的模式。针对掩码教授了位线矢量方法。

8. 发明申请

US20070256079A1 CONTEXT SELECTION AND ACTIVATION MECHANISM FOR ACTIVATING ONE OF A GROUP OF INACTIVE CONTEXTS IN A PROCESSOR CORE FOR SERVICING INTERRUPTS 有权
标题翻译：用于在一个处理器核心中激活一组不活动内容的服务中断的背景选择和激活机制
公开(公告)号：US20070256079A1
公开(公告)日：2007-11-01
申请号：US11566870
申请日：2006-12-05
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F9/46
CPC分类号： G06F9/461 , G06F9/4812 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.
摘要翻译：提供数据分组处理器中的逻辑系统用于选择和释放多个上下文中的一个。所选择和发布的上下文专用于使得能够处理对应于在数据分组处理中生成的中断并且待服务的中断服务例程。该系统包括用于确定所有上下文的控制状态的第一确定逻辑，用于确定上下文是否空闲的第二确定逻辑，用于选择上下文的选择逻辑和用于释放所选择的上下文的上下文释放机制。由逻辑系统确定所有上下文由不对分组处理负责的实体单独拥有，并且至少一个上下文是空闲的，触发所述至少一个空闲上下文中空闲的一个空闲上下文到负责的实体用于数据包处理。

9. 发明申请

US20070110090A1 METHOD AND APPARATUS FOR OVERFLOWING DATA PACKETS TO A SOFTWARE-CONTROLLED MEMORY WHEN THEY DO NOT FIT INTO A HARDWARE-CONTROLLED MEMORY 有权
标题翻译：将数据分组覆盖到不受硬件控制的存储器中的软件控制的存储器的方法和装置
公开(公告)号：US20070110090A1
公开(公告)日：2007-05-17
申请号：US11552764
申请日：2006-10-25
申请人： Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/54
CPC分类号： H04L49/9047 , G06F12/023 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L49/9078 , Y10S707/99953 , Y10S707/99956
摘要： A system for managing packets incoming to a data router has a local packet memory (LPM) mapped into pre-configured memory units, to store packets for processing, an external packet memory (EPM), a first storage system to store packets in the LPM, and a second storage system to store packets in the EPM. The system is characterized in that the first storage system attempts to store all incoming packets in the LPM, and for those packets that are not compatible with the LPM, relinquishes control to the second system, which stores the LPM-incompatible packets in the EPM.
摘要翻译：用于管理进入数据路由器的分组的系统具有映射到预先配置的存储器单元中的本地分组存储器（LPM），以存储用于处理的分组，外部分组存储器（EPM），第一存储系统以在LPM中存储分组以及用于在EPM中存储分组的第二存储系统。该系统的特征在于，第一个存储系统尝试将所有传入的数据包存储在LPM中，对于与LPM不兼容的那些数据包，放弃对EPM中存储LPM不兼容数据包的第二个系统的控制。

10. 发明申请

US20070074014A1 EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS 审中-公开
标题翻译：扩展的包装处理应用指导
公开(公告)号：US20070074014A1
公开(公告)日：2007-03-29
申请号：US11530945
申请日：2006-09-12
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F7/00
CPC分类号： G06F9/30003 , G06F9/30101 , G06F9/3851 , G06F9/3885 , G06F9/5016 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.
摘要翻译：公开了一种用于动态多流处理器的软件程序扩展。该扩展包括能够在分组管理组件和处理器的核心处理组件之间进行协调交互的指令集。该软件程序包括用于管理分组上传和下载进出存储器的部分，其一部分用于管理与排队和出队数据分组相关联的特定存储器分配和去分配，其一部分用于管理多个上下文的使用专用于处理单个数据包; 以及其一部分，用于管理与数据分组处理相关联的算术和其他上下文存储器功能的选择和利用。该扩展补充了用于特定用于具有独立于流处理器单元的分组管理单元的处理器的标准数据分组处理程序体系结构。

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