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1. 发明申请

US20090187739A1 Method and Apparatus for Improved Computer Load and Store Operations 审中-公开
标题翻译：用于改进计算机负载和存储操作的方法和装置
公开(公告)号：US20090187739A1
公开(公告)日：2009-07-23
申请号：US12411913
申请日：2009-03-26
申请人： Mario NEMIROVSKY , Enrique Musoll , Narendra Sankar , Stephen Melvin
发明人： Mario NEMIROVSKY , Enrique Musoll , Narendra Sankar , Stephen Melvin
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
摘要翻译：扩展了计算机系统中的加载和存储操作，以提供流加载和存储和掩蔽加载和存储。在Stream操作中，CPU执行Stream指令，该指令通过适当的参数指示存储器中的第一个地址或寄存器文件中的第一个寄存器，从开始读取数据实体，以及第一个地址或寄存器，从开始存储实体和一些要读写的实体。在屏蔽加载和屏蔽存储操作中，存储的掩码用于指示相对于第一个地址和寄存器进行加载和存储的模式。针对掩码教授了位线矢量方法。

2. 发明授权

US07280548B2 Method and apparatus for non-speculative pre-fetch operation in data packet processing 有权
标题翻译：数据包处理中非推测性预取操作的方法和装置
公开(公告)号：US07280548B2
公开(公告)日：2007-10-09
申请号：US11278890
申请日：2006-04-06
申请人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
摘要翻译：提供了一种系统，用于使得能够在分组处理器的即时分组处理之前的后台执行用于处理指令的非推测性预取操作。该系统包括用于接收数据分组并将其排入待处理的分组管理单元，用于处理数据分组的处理器单元，用于保存上下文寄存器的处理器核心存储器和用于处理的功能单元，用于保存多个指令线程的存储器以及用于将队列与指向开始指令线程的指针相关联的软件可配置硬件表。分组管理单元在处理器核心中选择用于处理数据分组的可用上下文，参考表格，并将指针传送到处理器，使得处理器能够对指令进行非推测性预取。

3. 发明授权

US07165257B2 Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts 有权
标题翻译：用于激活处理器核心中的一组非活动上下文中的一个用于服务中断的上下文选择和激活机制
公开(公告)号：US07165257B2
公开(公告)日：2007-01-16
申请号：US09927129
申请日：2001-08-10
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F9/46 , G06F3/00 , G06F9/00
CPC分类号： G06F9/461 , G06F9/4812 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.
摘要翻译：提供数据分组处理器中的逻辑系统用于选择和释放多个上下文中的一个。所选择和发布的上下文专用于使得能够处理对应于在数据分组处理中生成的中断并且待服务的中断服务例程。该系统包括用于确定所有上下文的控制状态的第一确定逻辑，用于确定上下文是否空闲的第二确定逻辑，用于选择上下文的选择逻辑和用于释放所选择的上下文的上下文释放机制。由逻辑系统确定所有上下文由不对分组处理负责的实体单独拥有，并且至少一个上下文是空闲的，触发所述至少一个空闲上下文中空闲的一个空闲上下文到负责的实体用于数据包处理。

4. 发明授权

US07197043B2 Method for allocating memory space for limited packet head and/or tail growth 有权
标题翻译：用于为有限的包头和/或尾部增长分配存储器空间的方法
公开(公告)号：US07197043B2
公开(公告)日：2007-03-27
申请号：US11278901
申请日：2006-04-06
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： H04J3/26
CPC分类号： H04L49/9073 , H04L49/90 , H04L49/901 , H04L49/9026 , H04L49/9047
摘要： A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
摘要翻译：提供了一种硬件/软件系统，用于以围绕要存储在存储器中的数据分组的缓冲区的形式分配存储器。硬件/软件系统包括：第一和第二寄存器，用于存储表示在一个寄存器中的单独的值，在要存储的数据分组的第一行之前的存储器的量，另一个存储在数据包的最后一行的量存储用于根据使用寄存器值计算的计算结果和要存储的数据分组的大小分配存储器的硬件机制，以及用于处理存储的数据分组并用于将任何新的增长数据写入到指定的缓冲区中的软件数据包。

5. 发明申请

US20060215679A1 METHOD FOR ALLOCATING MEMORY SPACE FOR LIMITED PACKET HEAD AND/OR TAIL GROWTH 有权
标题翻译：用于分配储存头和/或尾部生长的记忆空间的方法
公开(公告)号：US20060215679A1
公开(公告)日：2006-09-28
申请号：US11278901
申请日：2006-04-06
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , H04L49/90 , H04L49/901 , H04L49/9026 , H04L49/9047
摘要： A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
摘要翻译：提供了一种硬件/软件系统，用于以围绕要存储在存储器中的数据分组的缓冲区的形式分配存储器。硬件/软件系统包括：第一和第二寄存器，用于存储表示在一个寄存器中的单独的值，在要存储的数据分组的第一行之前的存储器的量，另一个存储在数据包的最后一行的量存储用于根据使用寄存器值计算的计算结果和要存储的数据分组的大小分配存储器的硬件机制，以及用于处理存储的数据分组并用于将任何新的增长数据写入到指定的缓冲区中的软件数据包。

6. 发明申请

US20070256079A1 CONTEXT SELECTION AND ACTIVATION MECHANISM FOR ACTIVATING ONE OF A GROUP OF INACTIVE CONTEXTS IN A PROCESSOR CORE FOR SERVICING INTERRUPTS 有权
标题翻译：用于在一个处理器核心中激活一组不活动内容的服务中断的背景选择和激活机制
公开(公告)号：US20070256079A1
公开(公告)日：2007-11-01
申请号：US11566870
申请日：2006-12-05
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F9/46
CPC分类号： G06F9/461 , G06F9/4812 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.
摘要翻译：提供数据分组处理器中的逻辑系统用于选择和释放多个上下文中的一个。所选择和发布的上下文专用于使得能够处理对应于在数据分组处理中生成的中断并且待服务的中断服务例程。该系统包括用于确定所有上下文的控制状态的第一确定逻辑，用于确定上下文是否空闲的第二确定逻辑，用于选择上下文的选择逻辑和用于释放所选择的上下文的上下文释放机制。由逻辑系统确定所有上下文由不对分组处理负责的实体单独拥有，并且至少一个上下文是空闲的，触发所述至少一个空闲上下文中空闲的一个空闲上下文到负责的实体用于数据包处理。

7. 发明申请

US20070110090A1 METHOD AND APPARATUS FOR OVERFLOWING DATA PACKETS TO A SOFTWARE-CONTROLLED MEMORY WHEN THEY DO NOT FIT INTO A HARDWARE-CONTROLLED MEMORY 有权
标题翻译：将数据分组覆盖到不受硬件控制的存储器中的软件控制的存储器的方法和装置
公开(公告)号：US20070110090A1
公开(公告)日：2007-05-17
申请号：US11552764
申请日：2006-10-25
申请人： Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/54
CPC分类号： H04L49/9047 , G06F12/023 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L49/9078 , Y10S707/99953 , Y10S707/99956
摘要： A system for managing packets incoming to a data router has a local packet memory (LPM) mapped into pre-configured memory units, to store packets for processing, an external packet memory (EPM), a first storage system to store packets in the LPM, and a second storage system to store packets in the EPM. The system is characterized in that the first storage system attempts to store all incoming packets in the LPM, and for those packets that are not compatible with the LPM, relinquishes control to the second system, which stores the LPM-incompatible packets in the EPM.
摘要翻译：用于管理进入数据路由器的分组的系统具有映射到预先配置的存储器单元中的本地分组存储器（LPM），以存储用于处理的分组，外部分组存储器（EPM），第一存储系统以在LPM中存储分组以及用于在EPM中存储分组的第二存储系统。该系统的特征在于，第一个存储系统尝试将所有传入的数据包存储在LPM中，对于与LPM不兼容的那些数据包，放弃对EPM中存储LPM不兼容数据包的第二个系统的控制。

8. 发明申请

US20070074014A1 EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS 审中-公开
标题翻译：扩展的包装处理应用指导
公开(公告)号：US20070074014A1
公开(公告)日：2007-03-29
申请号：US11530945
申请日：2006-09-12
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： G06F7/00
CPC分类号： G06F9/30003 , G06F9/30101 , G06F9/3851 , G06F9/3885 , G06F9/5016 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.
摘要翻译：公开了一种用于动态多流处理器的软件程序扩展。该扩展包括能够在分组管理组件和处理器的核心处理组件之间进行协调交互的指令集。该软件程序包括用于管理分组上传和下载进出存储器的部分，其一部分用于管理与排队和出队数据分组相关联的特定存储器分配和去分配，其一部分用于管理多个上下文的使用专用于处理单个数据包; 以及其一部分，用于管理与数据分组处理相关联的算术和其他上下文存储器功能的选择和利用。该扩展补充了用于特定用于具有独立于流处理器单元的分组管理单元的处理器的标准数据分组处理程序体系结构。

9. 发明申请

US20060215670A1 METHOD AND APPARATUS FOR NON-SPECULATIVE PRE-FETCH OPERATION IN DATA PACKET PROCESSING 有权
标题翻译：数据分组处理中非调制型预充电操作的方法和装置
公开(公告)号：US20060215670A1
公开(公告)日：2006-09-28
申请号：US11278890
申请日：2006-04-06
申请人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
发明人： Nandakumar Sampath , Enrique Musoll , Stephen Melvin , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
摘要翻译：提供了一种系统，用于使得能够在分组处理器的即时分组处理之前的后台执行用于处理指令的非推测性预取操作。该系统包括用于接收数据分组并将其排入待处理的分组管理单元，用于处理数据分组的处理器单元，用于保存上下文寄存器的处理器核心存储器和用于处理的功能单元，用于保存多个指令线程的存储器以及用于将队列与指向开始指令线程的指针相关联的软件可配置硬件表。分组管理单元在处理器核心中选择用于处理数据分组的可用上下文，参考表格，并将指针传送到处理器，使得处理器能够对指令进行非推测性预取。

10. 发明授权

US07139901B2 Extended instruction set for packet processing applications 有权
公开(公告)号：US07139901B2
公开(公告)日：2006-11-21
申请号：US09948919
申请日：2001-09-07
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： H04L12/28 , G06F15/00 , G06F7/38
CPC分类号： G06F9/30003 , G06F9/30101 , G06F9/3851 , G06F9/3885 , G06F9/5016 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.

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