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1. 发明申请

US20080270757A1 Fetch and Dispatch Disassociation Apparatus for Multistreaming Processors 有权
标题翻译：用于多数据流处理器的获取和调度关联装置
公开(公告)号：US20080270757A1
公开(公告)日：2008-10-30
申请号：US12173560
申请日：2008-07-15
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.
摘要翻译：动态多流处理器具有指令队列，对应于指令流的每个指令队列和执行单元。动态多流处理器还具有调度阶段，用于从一个指令队列中选择至少一个指令，并将所选择的至少一个指令发送到执行单元之一。最后，动态多流处理器具有与每个指令队列相关联的用于指示每个队列中的指令数量的队列计数器，以及与每个指令队列相关联的提取计数器，用于指示当相关联的指令时从其获得指令的地址队列不满。动态多数据流处理器还可以具有用于指示下一个指令地址的读取计数器，当相关联的指令队列未满时，该指令地址从其获得至少一个指令。动态多流处理器还可以具有用于指示下一个指令地址的第二计数器。

2. 发明申请

US20070260852A1 FETCH AND DISPATCH DISASSOCIATION APPARATUS FOR MULTI-STREAMING PROCESSORS 有权
标题翻译：多流程处理器的FETCH和DISPATCH分配设备
公开(公告)号：US20070260852A1
公开(公告)日：2007-11-08
申请号：US11539322
申请日：2006-10-06
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enrique Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

3. 发明授权

US07139898B1 Fetch and dispatch disassociation apparatus for multistreaming processors 有权
标题翻译：用于多数据流处理器的获取和调度分离装置
公开(公告)号：US07139898B1
公开(公告)日：2006-11-21
申请号：US09706154
申请日：2000-11-03
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/312
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

4. 发明授权

US07406586B2 Fetch and dispatch disassociation apparatus for multi-streaming processors 有权
标题翻译：用于多流处理器的获取和调度分离装置
公开(公告)号：US07406586B2
公开(公告)日：2008-07-29
申请号：US11539322
申请日：2006-10-06
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流，用于向一组执行单元选择和分派指令的调度阶段，具有与多个中的每个流相关联的一个队列的一组指令队列的流，并且位于指令高速缓存和调度阶段之间的流水线中，以及用于在每个周期中选择流以从指令高速缓存获取指令的选择系统。处理器的特征在于，选择系统在每个周期中选择一个或多个流，用于从指令高速缓存取出指令，并且在每个周期中为其取指令的流的数量少于流数在多个流中。

5. 发明授权

US07502876B1 Background memory manager that determines if data structures fits in memory with memory state transactions map 有权
标题翻译：后台存储器管理器，用于确定数据结构是否与存储器状态事务映射相匹配
公开(公告)号：US07502876B1
公开(公告)日：2009-03-10
申请号：US09602279
申请日：2000-06-23
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F13/00 , G06F12/08 , G06F12/00
CPC分类号： G06F12/023 , G06F13/28
摘要： A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. The BMM manages the memory, determining if each data structure fits into the memory, deciding exactly where to place the data structure in memory, performing all data transfers between the outside device and the memory, and maintaining the memory state map according to memory transactions made, and informing the processor of new data and its location. In preferred embodiments the BMM, in the process of storing data structures into the memory, provides an identifier for each structure to the processor. The system is particularly applicable to Internet packet processing in packet routers.
摘要翻译：用于管理数据处理系统中的存储器的后台存储器管理器（BMM）具有用于向外部设备传送数据和从外部设备传送数据到存储器和从存储器传送数据的存储器的电路，与存储器相关联的存储器状态映射以及到处理器的通信链路。 BMM管理存储器，确定每个数据结构是否适合存储器，准确地确定数据结构放置在存储器中的位置，在外部设备和存储器之间执行所有数据传输，并根据存储器事务来保持存储器状态映射并通知处理器新数据及其位置。在优选实施例中，BMM在将数据结构存储到存储器中的过程中向处理器提供每个结构的标识符。该系统特别适用于分组路由器中的因特网分组处理。

6. 发明授权

US07715410B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07715410B2
公开(公告)日：2010-05-11
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F13/00 , G06F12/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动所识别的分组的处理，完成的分组的下载或用于重新选择所选择的分组标识符的选择逻辑。

7. 发明授权

US07032226B1 Methods and apparatus for managing a buffer of events in the background 有权
标题翻译：用于管理后台事件缓冲区的方法和装置
公开(公告)号：US07032226B1
公开(公告)日：2006-04-18
申请号：US09608750
申请日：2000-06-30
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

8. 发明申请

US20050081214A1 Interstream control and communications for multi-streaming digital processors 有权
标题翻译：多流数字处理器的串流控制和通信
公开(公告)号：US20050081214A1
公开(公告)日：2005-04-14
申请号：US10921077
申请日：2004-08-18
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F3/00
CPC分类号： G06F9/485 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/462 , G06F9/468
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map. In this mechanism each stream maintains and edits a bitmap granting or withdrawing control privileges for each other stream, the settings valid for any stream but a Master stream, which will ignore the settings.
摘要翻译：多流处理器具有用于流传输一个或多个指令线程的多个流，用于从流处理指令的一组功能资源; 以及互流控制机制，由此任何流可以影响任何其他流的操作。在各种实施例中，互流控制机制包括用于完成一个或多个启用或禁用另一个流，将另一个流进入睡眠模式或从睡眠模式唤醒另一个流的机制，为相对于对功能资源的访问设置另一个流的优先级，以及允许另一个流阻止访问功能资源。教授主模式，其中一个流被授予主状态，从而可以相对于其他流发挥任何和所有可用的控制机制，而不受任何流的干扰。还教授监督模式，其中可以从最小到完全控制授予控制，其中控制流的遵从性可以改变或撤销控制权限。公开了各种机制，包括其中通过至少一个片上位图记录和修改主状态和跨流控制层级的机制。在这种机制中，每个流维护和编辑一个位图，为每个其他流授予或撤销控制权限，这些设置对任何流都有效，但是主流将忽略这些设置。

9. 发明申请

US20060225080A1 METHODS AND APPARATUS FOR MANAGING A BUFFER OF EVENTS IN THE BACKGROUND 有权
标题翻译：在背景下管理事件缓冲的方法和装置
公开(公告)号：US20060225080A1
公开(公告)日：2006-10-05
申请号：US11278747
申请日：2006-04-05
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

10. 发明申请

US20060159104A1 QUEUEING SYSTEM FOR PROCESSORS IN PACKET ROUTING OPERATIONS 有权
标题翻译：分组路由操作中处理器的队列系统
公开(公告)号：US20060159104A1
公开(公告)日：2006-07-20
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，在处理期间用于分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

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