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1. 发明授权

US07715410B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07715410B2
公开(公告)日：2010-05-11
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F13/00 , G06F12/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动所识别的分组的处理，完成的分组的下载或用于重新选择所选择的分组标识符的选择逻辑。

2. 发明申请

US20100103938A1 Context Sharing Between A Streaming Processing Unit (SPU) and A Packet Management Unit (PMU) In A Packet Processing Environment 有权
标题翻译：在分组处理环境中的流处理单元（SPU）和分组管理单元（PMU）之间的上下文共享
公开(公告)号：US20100103938A1
公开(公告)日：2010-04-29
申请号：US12649132
申请日：2009-12-29
申请人： Enrique MUSOLL , Mario Nemirovsky
发明人： Enrique MUSOLL , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/12 , H04L69/22
摘要： A context-selection mechanism is provided for selecting a best context from a pool of contexts for processing a data packet. The context selection mechanism comprises, an interface for communicating with a multi-streaming processor; circuitry for computing input data into a result value according to logic rule and for selecting a context based on the computed value and a loading mechanism for preloading the packet information into the selected context for subsequent processing. The computation of the input data functions to enable identification and selection of a best context for processing a data packet according to the logic rule at the instant time such that a multitude of subsequent context selections over a period of time acts to balance load pressure on functional units housed within the multi-streaming processor and required for packet processing. In preferred aspects, programmable singular or multiple predictive rules of logic are utilized in the selection process.
摘要翻译：提供了一种上下文选择机制，用于从用于处理数据分组的上下文池中选择最佳上下文。上下文选择机制包括：用于与多流处理器通信的接口; 用于根据逻辑规则将输入数据计算到结果值中并基于所计算的值来选择上下文的电路，以及用于将分组信息预加载到所选择的上下文中用于后续处理的加载机制。输入数据的计算功能用于根据逻辑规则来识别和选择用于处理数据分组的最佳上下文，使得在一段时间内多个随后的上下文选择用于平衡负载压力对功能性单元被容纳在多流处理器内并且需要进行数据包处理。在优选方面，在选择过程中利用可编程单数或多重预测逻辑规则。

3. 发明授权

US07197043B2 Method for allocating memory space for limited packet head and/or tail growth 有权
标题翻译：用于为有限的包头和/或尾部增长分配存储器空间的方法
公开(公告)号：US07197043B2
公开(公告)日：2007-03-27
申请号：US11278901
申请日：2006-04-06
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： H04J3/26
CPC分类号： H04L49/9073 , H04L49/90 , H04L49/901 , H04L49/9026 , H04L49/9047
摘要： A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
摘要翻译：提供了一种硬件/软件系统，用于以围绕要存储在存储器中的数据分组的缓冲区的形式分配存储器。硬件/软件系统包括：第一和第二寄存器，用于存储表示在一个寄存器中的单独的值，在要存储的数据分组的第一行之前的存储器的量，另一个存储在数据包的最后一行的量存储用于根据使用寄存器值计算的计算结果和要存储的数据分组的大小分配存储器的硬件机制，以及用于处理存储的数据分组并用于将任何新的增长数据写入到指定的缓冲区中的软件数据包。

4. 发明申请

US20060215679A1 METHOD FOR ALLOCATING MEMORY SPACE FOR LIMITED PACKET HEAD AND/OR TAIL GROWTH 有权
标题翻译：用于分配储存头和/或尾部生长的记忆空间的方法
公开(公告)号：US20060215679A1
公开(公告)日：2006-09-28
申请号：US11278901
申请日：2006-04-06
申请人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
发明人： Enrique Musoll , Mario Nemirovsky , Stephen Melvin
IPC分类号： H04L12/56
CPC分类号： H04L49/9073 , H04L49/90 , H04L49/901 , H04L49/9026 , H04L49/9047
摘要： A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
摘要翻译：提供了一种硬件/软件系统，用于以围绕要存储在存储器中的数据分组的缓冲区的形式分配存储器。硬件/软件系统包括：第一和第二寄存器，用于存储表示在一个寄存器中的单独的值，在要存储的数据分组的第一行之前的存储器的量，另一个存储在数据包的最后一行的量存储用于根据使用寄存器值计算的计算结果和要存储的数据分组的大小分配存储器的硬件机制，以及用于处理存储的数据分组并用于将任何新的增长数据写入到指定的缓冲区中的软件数据包。

5. 发明授权

US07076630B2 Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management 有权
标题翻译：用于在背景备忘录管理中分配和分配连续的存储块的方法和装置
公开(公告)号：US07076630B2
公开(公告)日：2006-07-11
申请号：US09881934
申请日：2001-06-14
申请人： Enrique Musoll , Mario Nemirovsky
发明人： Enrique Musoll , Mario Nemirovsky
IPC分类号： G06F12/08
CPC分类号： H04L49/9047 , G06F12/023 , H04L49/90 , H04L49/901
摘要： A system for allocating storage of incoming data packets into a memory of a packet processor has a first facility mapping a first block of memory of a fixed block size in bytes into an ordered plurality of atomic pages comprising each a fixed byte size, a second facility mapping the same block of memory into ordered virtual pages of different sizes, ranging from a smaller virtual page size equal to the atomic page size up to a larger virtual page size equal to the fixed block size, a third facility to allocate virtual pages as unavailable for storage or de-allocate virtual pages as available for storage, a fourth facility to receive a data packet, ascertain packet size for the received packet, and to determine fit by checking allocation state for virtual pages of a smallest size that is equal to or larger than the packet size, then allocation state for next larger virtual pages, and so on, until a de-allocated, available virtual page is found; and a fifth facility to select a virtual page to store the packet, and to update and mark associated atomic pages in the selected virtual page as available or unavailable for storage, in an ordered manner. The system is characterized in that, after each selection by the fifth facility, state of all atomic and virtual pages is updated.
摘要翻译：用于将输入数据分组的存储分配到分组处理器的存储器中的系统具有将固定块大小（以字节为单位）的第一存储器块映射到包括固定字节大小的有序多个原子页面中的第一设施，第二设施将相同的内存块映射到不同大小的有序虚拟页面，范围从等于原子页面大小的较小虚拟页面大小到等于固定块大小的较大虚拟页面大小，将虚拟页面分配为不可用的第三个设施用于存储或取消分配可用于存储的虚拟页面，接收数据分组的第四设备，确定所接收的分组的分组大小，以及通过检查等于或等于最小尺寸的虚拟页面的虚拟页面的分配状态来确定拟合大于分组大小，然后分配下一个较大虚拟页面的状态，等等，直到找到解除分配的可用虚拟页面; 以及用于选择存储分组的虚拟页面的第五设施，并且以有序的方式更新和标记所选择的虚拟页面中可用或不可用于存储的相关原子页面。该系统的特征在于，在通过第五设施的每次选择之后，更新所有原子和虚拟页面的状态。

6. 发明授权

US07035998B1 Clustering stream and/or instruction queues for multi-streaming processors 有权
标题翻译：用于多流处理器的聚集流和/或指令队列
公开(公告)号：US07035998B1
公开(公告)日：2006-04-25
申请号：US09706157
申请日：2000-11-03
申请人： Mario Nemirovsky , Stephen W. Melvin , Nandakumar Sampath , Enrique Musoll , Hector Urdaneta
发明人： Mario Nemirovsky , Stephen W. Melvin , Nandakumar Sampath , Enrique Musoll , Hector Urdaneta
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3891
摘要： A pipelined multistreaming processor has an instruction source, a first cluster of a plurality of streams fetching instructions from the instruction source, a second cluster of a plurality of streams fetching instructions from the instruction source, dedicated instruction queues for individual streams in each cluster, a first dedicated dispatch stage in the first cluster for dispatching instructions to execution units, and a second dedicated dispatch stage in the second cluster for selecting and dispatching instructions to execution units. The processor is characterized in that the clusters operate independently, with the dedicated dispatch stage taking instructions only from the instruction queues in the individual clusters to which the dispatch stages are dedicated. In preferred embodiments there are dedicated fetch and dispatch stages for streams in the clusters, and dedicated execution units to which instructions may be dispatched.
摘要翻译：流水线多流处理器具有指令源，从指令源获取指令的多个流的第一簇，从指令源获取指令的多个流的第二簇，每个簇中的各个流的专用指令队列，用于向执行单元发送指令的第一集群中的第一专用调度阶段，以及用于向执行单元选择和分派指令的第二集群中的第二专用调度阶段。处理器的特征在于，集群独立地操作，专用调度阶段仅从调度阶段专用的各个集群中的指令队列获取指令。在优选实施例中，存在用于集群中的流的专用获取和分派阶段以及可以向其发送指令的专用执行单元。

7. 发明授权

US07032226B1 Methods and apparatus for managing a buffer of events in the background 有权
标题翻译：用于管理后台事件缓冲区的方法和装置
公开(公告)号：US07032226B1
公开(公告)日：2006-04-18
申请号：US09608750
申请日：2000-06-30
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

8. 发明申请

US20050081214A1 Interstream control and communications for multi-streaming digital processors 有权
标题翻译：多流数字处理器的串流控制和通信
公开(公告)号：US20050081214A1
公开(公告)日：2005-04-14
申请号：US10921077
申请日：2004-08-18
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Narendra Sankar
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F3/00
CPC分类号： G06F9/485 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/462 , G06F9/468
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map. In this mechanism each stream maintains and edits a bitmap granting or withdrawing control privileges for each other stream, the settings valid for any stream but a Master stream, which will ignore the settings.
摘要翻译：多流处理器具有用于流传输一个或多个指令线程的多个流，用于从流处理指令的一组功能资源; 以及互流控制机制，由此任何流可以影响任何其他流的操作。在各种实施例中，互流控制机制包括用于完成一个或多个启用或禁用另一个流，将另一个流进入睡眠模式或从睡眠模式唤醒另一个流的机制，为相对于对功能资源的访问设置另一个流的优先级，以及允许另一个流阻止访问功能资源。教授主模式，其中一个流被授予主状态，从而可以相对于其他流发挥任何和所有可用的控制机制，而不受任何流的干扰。还教授监督模式，其中可以从最小到完全控制授予控制，其中控制流的遵从性可以改变或撤销控制权限。公开了各种机制，包括其中通过至少一个片上位图记录和修改主状态和跨流控制层级的机制。在这种机制中，每个流维护和编辑一个位图，为每个其他流授予或撤销控制权限，这些设置对任何流都有效，但是主流将忽略这些设置。

9. 发明授权

US08081645B2 Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment 有权
标题翻译：分组处理环境中的流处理单元（SPU）和分组管理单元（PMU）之间的上下文共享
公开(公告)号：US08081645B2
公开(公告)日：2011-12-20
申请号：US12649132
申请日：2009-12-29
申请人： Enrique Musoll , Mario Nemirovsky
发明人： Enrique Musoll , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/12 , H04L69/22
摘要： A method for processing multiple data packets includes receiving from a network interface, at a packet management unit (PMU), a data packet for processing, and determining whether to store or drop the data packet. The method further includes queueing the data packet in a queue within a queueing system and preloading a portion of the data packet into a context from a pool of contexts in a stream processing unit (SPU). The queued data packet referenced by the context is processed by the SPU and outputted to the network interface.
摘要翻译：一种用于处理多个数据分组的方法，包括从分组管理单元（PMU）的网络接口接收用于处理的数据分组，以及确定是否存储或丢弃数据分组。该方法还包括将数据分组排队在排队系统内的队列中，并将数据分组的一部分从流处理单元（SPU）中的上下文池预加载到上下文中。由上下文引用的排队数据包由SPU处理并输出到网络接口。

10. 发明申请

US20090187739A1 Method and Apparatus for Improved Computer Load and Store Operations 审中-公开
标题翻译：用于改进计算机负载和存储操作的方法和装置
公开(公告)号：US20090187739A1
公开(公告)日：2009-07-23
申请号：US12411913
申请日：2009-03-26
申请人： Mario NEMIROVSKY , Enrique Musoll , Narendra Sankar , Stephen Melvin
发明人： Mario NEMIROVSKY , Enrique Musoll , Narendra Sankar , Stephen Melvin
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
摘要翻译：扩展了计算机系统中的加载和存储操作，以提供流加载和存储和掩蔽加载和存储。在Stream操作中，CPU执行Stream指令，该指令通过适当的参数指示存储器中的第一个地址或寄存器文件中的第一个寄存器，从开始读取数据实体，以及第一个地址或寄存器，从开始存储实体和一些要读写的实体。在屏蔽加载和屏蔽存储操作中，存储的掩码用于指示相对于第一个地址和寄存器进行加载和存储的模式。针对掩码教授了位线矢量方法。

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