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1. 发明授权

US07968270B2 Process of making a semiconductor device using multiple antireflective materials 有权
标题翻译：制造使用多种抗反射材料的半导体器件的工艺
公开(公告)号：US07968270B2
公开(公告)日：2011-06-28
申请号：US12197571
申请日：2008-08-25
申请人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
发明人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
IPC分类号： G03F7/11 , G03F7/40
CPC分类号： G03F7/091 , Y10S438/952
摘要： A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.
摘要翻译：一种光刻结构，主要由以下部分组成：设置在基板上的有机抗反射材料; 气相沉积的RCHX材料，其中R是选自Si，Ge，B，Sn，Fe和Ti中的一种或多种元素，并且其中X不存在或者是选自以下的一种或多种元素： O，N，S和F; 以及设置在RCHX材料上的光致抗蚀剂材料。本发明还涉及制造光刻结构的方法，并且使用该结构来图案化衬底。

2. 发明申请

US20080311508A1 PROCESS OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE ANTIREFLECTIVE MATERIALS 有权
标题翻译：使用多种抗反射材料制备半导体器件的工艺
公开(公告)号：US20080311508A1
公开(公告)日：2008-12-18
申请号：US12197571
申请日：2008-08-25
申请人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
发明人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
IPC分类号： G03F7/20 , C23C16/00 , G03C1/735 , G03C1/73
CPC分类号： G03F7/091 , Y10S438/952
摘要： A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.
摘要翻译：一种光刻结构，主要由以下部分组成：设置在基板上的有机抗反射材料; 气相沉积的RCHX材料，其中R是选自Si，Ge，B，Sn，Fe和Ti中的一种或多种元素，并且其中X不存在或者是选自以下的一种或多种元素： O，N，S和F; 以及设置在RCHX材料上的光致抗蚀剂材料。本发明还涉及制造光刻结构的方法，并且使用该结构来图案化衬底。

3. 发明授权

US07485573B2 Process of making a semiconductor device using multiple antireflective materials 失效
标题翻译：制造使用多种抗反射材料的半导体器件的工艺
公开(公告)号：US07485573B2
公开(公告)日：2009-02-03
申请号：US11356027
申请日：2006-02-17
申请人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
发明人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
IPC分类号： H01L21/4763
CPC分类号： G03F7/091 , Y10S438/952
摘要： A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.
摘要翻译：一种光刻结构，主要由以下部分组成：设置在基板上的有机抗反射材料; 气相沉积的RCHX材料，其中R是选自Si，Ge，B，Sn，Fe和Ti中的一种或多种元素，并且其中X不存在或者是选自以下的一种或多种元素： O，N，S和F; 以及设置在RCHX材料上的光致抗蚀剂材料。本发明还涉及制造光刻结构的方法，并且使用该结构来图案化衬底。

4. 发明申请

US20090311855A1 METHOD OF FABRICATING A GATE STRUCTURE 审中-公开
标题翻译：制作门结构的方法
公开(公告)号：US20090311855A1
公开(公告)日：2009-12-17
申请号：US12544425
申请日：2009-08-20
申请人： Richard A. Bruff , Richard A. Conti , Denise Pendleton-Lipinski , Amanda L. Tessier , Brian L. Tessier , Yun-Yu Wang , Daewon Yang , Chienfan Yu
发明人： Richard A. Bruff , Richard A. Conti , Denise Pendleton-Lipinski , Amanda L. Tessier , Brian L. Tessier , Yun-Yu Wang , Daewon Yang , Chienfan Yu
IPC分类号： H01L21/28
CPC分类号： H01L21/823807 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823864 , H01L29/7843
摘要： A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.
摘要翻译：提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。设置在基板上的栅极结构包括多个栅极。多个栅极中的每一个与相邻栅极分开一垂直空间。该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

5. 发明申请

US20090101980A1 METHOD OF FABRICATING A GATE STRUCTURE AND THE STRUCTURE THEREOF 审中-公开
标题翻译：制造门式结构的方法及其结构
公开(公告)号：US20090101980A1
公开(公告)日：2009-04-23
申请号：US11875222
申请日：2007-10-19
申请人： Richard A. Bruff , Richard A. Conti , Denise Pendleton-Lipinski , Amanda L. Tessier , Brian L. Tessier , Yun-Yu Wang , Daewon Yang , Chienfan Yu
发明人： Richard A. Bruff , Richard A. Conti , Denise Pendleton-Lipinski , Amanda L. Tessier , Brian L. Tessier , Yun-Yu Wang , Daewon Yang , Chienfan Yu
IPC分类号： H01L27/088 , H01L21/3205
CPC分类号： H01L21/823807 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823864 , H01L29/7843
摘要： A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.
摘要翻译：提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。设置在基板上的栅极结构包括多个栅极。多个栅极中的每一个与相邻栅极分开一垂直空间。该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

6. 发明授权

US07491660B2 Method of forming nitride films with high compressive stress for improved PFET device performance 失效
标题翻译：形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法
公开(公告)号：US07491660B2
公开(公告)日：2009-02-17
申请号：US11873721
申请日：2007-10-17
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469 , C23C16/00 , C23C14/10 , C23C14/00
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译：提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。这种压应力允许改进PFET中的器件性能。使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。氮化物层的厚度在约300-2000埃的范围内。

7. 发明授权

US07462527B2 Method of forming nitride films with high compressive stress for improved PFET device performance 失效
标题翻译：形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法
公开(公告)号：US07462527B2
公开(公告)日：2008-12-09
申请号：US11160705
申请日：2005-07-06
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译：提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。这种压应力允许改进PFET中的器件性能。使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。氮化物层的厚度在约300-2000埃的范围内。

8. 发明申请

US20080286545A1 MASK HAVING IMPLANT STOPPING LAYER 审中-公开
标题翻译：掩蔽具有植入物停留层
公开(公告)号：US20080286545A1
公开(公告)日：2008-11-20
申请号：US12145922
申请日：2008-06-25
申请人： Katherina Babich , Todd C. Bailey , Richard A. Conti , Ryan P. Deschner
发明人： Katherina Babich , Todd C. Bailey , Richard A. Conti , Ryan P. Deschner
IPC分类号： B32B7/02
CPC分类号： H01L21/26513 , H01L21/266 , Y10T428/24992
摘要： Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.
摘要翻译：形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

9. 发明授权

US07179760B2 Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same 失效
标题翻译：双层盖结构，包括用于导电金属化的HDP / bHDP膜及其制造方法
公开(公告)号：US07179760B2
公开(公告)日：2007-02-20
申请号：US10908833
申请日：2005-05-27
申请人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.
摘要翻译：本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层）选择性。

10. 发明授权

US06667504B1 Self-aligned buried strap process using doped HDP oxide 失效
标题翻译：使用掺杂HDP氧化物的自对准掩埋工艺
公开(公告)号：US06667504B1
公开(公告)日：2003-12-23
申请号：US10249228
申请日：2003-03-24
申请人： Jochen Beintner , Wolfgang Bergner , Richard A. Conti , Andreas Knorr , Rolf Weis
发明人： Jochen Beintner , Wolfgang Bergner , Richard A. Conti , Andreas Knorr , Rolf Weis
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10864 , H01L29/945
摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.
摘要翻译：本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电埋在衬底中的邻近沟槽顶部氧化物的衬底。沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

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