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1. 发明授权

US06687167B2 EEPROM flash memory erasable line by line 有权
标题翻译： EEPROM闪存可逐行删除
公开(公告)号：US06687167B2
公开(公告)日：2004-02-03
申请号：US10225513
申请日：2002-08-20
申请人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
发明人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/16
摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
摘要翻译：一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和下分支。以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为下拉和下部分支作为上拉。

2. 发明授权

US06535428B2 Sensing circuit for memory cells 有权
标题翻译：存储单元的感应电路
公开(公告)号：US06535428B2
公开(公告)日：2003-03-18
申请号：US09882535
申请日：2001-06-14
申请人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
发明人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C11/5642
摘要： A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
摘要翻译：一种用于感测存储单元的感测电路，所述感测电路具有可电连接到所述存储单元以接收存储单元电流的第一电路分支，所述第一电路支路具有至少一个第一晶体管，当所述第一电路支路连接到存储器单元基本上以共源共栅配置耦合到存储器单元。偏置电流发生器与第一晶体管可操作地相关联，以迫使偏置电流流过其中。

3. 发明授权

US06667903B2 Programming method for a multilevel memory cell 有权
公开(公告)号：US06667903B2
公开(公告)日：2003-12-23
申请号：US10017502
申请日：2001-12-14
申请人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
发明人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5635 , G11C17/146
摘要： It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

4. 发明授权

US06473340B1 Reading method and circuit for a non-volatile memory 有权
标题翻译：用于非易失性存储器的读取方法和电路
公开(公告)号：US06473340B1
公开(公告)日：2002-10-29
申请号：US09699043
申请日：2000-10-27
申请人： Marco Pasotti , Giovanni Guaitini , Pier Luigi Rolandi , Guido De Sandre
发明人： Marco Pasotti , Giovanni Guaitini , Pier Luigi Rolandi , Guido De Sandre
IPC分类号： G11C1300
CPC分类号： G11C11/5642 , G11C16/28
摘要： A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.
摘要翻译：一种读取电路，具有经由阵列位线连接到阵列存储单元的阵列分支，其内容将被读取; 通过参考位线连接到提供参考电流的电流发生器级的参考支路; 连接到阵列支路和参考支路的电流/电压转换器级，并且在阵列节点和参考节点处分别提供与分别在阵列支路中流动的电流相关联的阵列电位和参考电位，在参考分支中; 连接到阵列节点的比较器级和用于比较阵列和参考电位的参考节点; 布置在所述阵列节点和所述比较器台之间并且可选择地可操作地采样和保持所述阵列电位的采样和保持级; 以及用于关闭阵列分支的关闭阶段。

5. 发明授权

US06622106B2 Device for testing and calibrating the oscillation frequency of an integrated oscillator 有权
标题翻译：用于测试和校准集成振荡器的振荡频率的装置
公开(公告)号：US06622106B2
公开(公告)日：2003-09-16
申请号：US09833754
申请日：2001-04-11
申请人： Alessandro Rocchi , Marco Bisio , Guido De Sandre , Giovanni Guaitini , Marco Pasotti , Pier Luigi Rolandi
发明人： Alessandro Rocchi , Marco Bisio , Guido De Sandre , Giovanni Guaitini , Marco Pasotti , Pier Luigi Rolandi
IPC分类号： H03B500
CPC分类号： G01R31/2824
摘要： A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.
摘要翻译：一种用于测试和校准集成振荡器电路的振荡频率的数字装置，所述测试和校准装置具有至少第一和第二控制参数，所述至少第一和第二控制参数对应于为集成振荡器寻找的振荡频率的预定值范围的极限值并且其包括用于比较已知持续时间的信号和来自集成振荡器电路的信号的比较电路; 连接到比较电路的电路，用于产生来自集成振荡电路的信号的校准值; 以及用于强制将来自集成振荡器电路的信号的最终校准值存储到集成振荡器电路的存储和控制部分的电路。

6. 发明授权

US06400607B1 Reading circuit for a non-volatile memory 有权
标题翻译：非易失性存储器的读取电路
公开(公告)号：US06400607B1
公开(公告)日：2002-06-04
申请号：US09699304
申请日：2000-10-27
申请人： Marco Pasotti , Giovanni Guaitini , Pier Luigi Rolandi , Guido De Sandre
发明人： Marco Pasotti , Giovanni Guaitini , Pier Luigi Rolandi , Guido De Sandre
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C11/5642
摘要： A reading circuit having an array branch connected to a multi-level array memory cell; a reference branch connected to a reference memory cell; a current/voltage converter stage formed of a current mirror having a variable mirror ratio, connected to the array and reference branches, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated respectively to the currents flowing in the array branch and in the reference branch; and a comparator stage having a first and a second input connected to the array and reference nodes for comparing with one another the array and reference potentials.
摘要翻译：一种读取电路，具有连接到多级阵列存储单元的阵列分支; 连接到参考存储单元的参考分支; 电流/电压转换器级由具有可变镜像比的电流镜形成，连接到阵列和参考分支，并在阵列节点和参考节点分别提供阵列电位和参考电位，其分别与在阵列分支和参考分支中流动的电流; 以及比较器级，其具有连接到阵列的第一和第二输入以及用于彼此比较阵列和参考电位的参考节点。

7. 发明授权

US06381177B1 Method for controlled soft programming of non-volatile memory cells, in particular of the flash EEPROM and EPROM type 有权
标题翻译：用于非易失性存储单元的受控软编程的方法，特别是闪存EEPROM和EPROM类型的方法
公开(公告)号：US06381177B1
公开(公告)日：2002-04-30
申请号：US09699309
申请日：2000-10-27
申请人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi
发明人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi
IPC分类号： G11C1600
CPC分类号： G11C16/12
摘要： A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line. The method includes supplying at least one soft programming pulse to the plurality of memory cells for a time interval. In this step, a bulk voltage with a rising negative ramp is applied to the common bulk line for the time interval. By this means, the threshold voltage of the cells is increased by body effect, and initially only the most depleted cells are soft programmed, with a limited drain current. Subsequently, when the bulk voltage increases, the cells with a higher threshold voltage are also soft programmed, until all the cells have reached the required minimum threshold value.
摘要翻译：一种用于多个非易失性存储器单元的受控软编程的方法，其具有彼此连接的批量端子和公共批量线。该方法包括在一段时间间隔内向多个存储器单元提供至少一个软编程脉冲。在该步骤中，具有上升负斜率的体电压在时间间隔上被施加到公共批量线。通过这种方式，电池的阈值电压由于体效应而增加，并且最初只有最耗尽的电池被软编程，具有有限的漏极电流。随后，当体电压增加时，具有较高阈值电压的单元也被软编程，直到所有单元达到所需的最小阈值。

8. 发明授权

US06469934B2 Soft programming method for non-volatile memory cells 有权
标题翻译：非易失性存储单元的软编程方法
公开(公告)号：US06469934B2
公开(公告)日：2002-10-22
申请号：US09738253
申请日：2000-12-14
申请人： Guido de Sandre , Marco Pasotti , Pier Luigi Rolandi
发明人： Guido de Sandre , Marco Pasotti , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/3468
摘要： The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.
摘要翻译：优化的软编程方法用于由多个被分组成扇区的单元组成的存储器中。属于单个扇区的单元具有连接到多个字线的栅极端子和连接到多个局部位线的漏极端子。软编程方法包括在扇区中选择至少一个局部位线，同时选择同一扇区中的所有字线。相应的栅极电压被施加到所有字线，而具有预定值的恒定漏极电压被施加到局部位线。

9. 发明授权

US6163483A Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed 有权
标题翻译：并行编程电路非易失性存储单元，具有可编程速度
公开(公告)号：US6163483A
公开(公告)日：2000-12-19
申请号：US447531
申请日：1999-11-23
申请人： Marco Pasotti , Roberto Canegallo , Giovanni Guaitini , Pier Luigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Giovanni Guaitini , Pier Luigi Rolandi
IPC分类号： G11C16/12 , G11C7/00
CPC分类号： G11C16/12
摘要： A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.
摘要翻译：一种具有电流镜电路的电路，具有第一节点和第二节点，分别连接到可控电流源和连接到所选存储器单元的漏极端子的公共节点。第一运算放大器具有连接到第一节点和第二节点的输入，以及连接到所选择的存储器单元的控制端子并形成电路输出的输出。第二运算放大器具有连接到斜坡发生器的第一输入端，连接到电路输出端的第二输入端，以及连接到可控电流源的控制输入端的输出端。因此，两个负反馈环路将所选择的存储单元的漏极端子保持在足以编程的电压值，并且以导致所选择的存储单元写入的斜坡电压馈送存储单元的控制端子。在第二节点和公共节点之间存在偏置源，使得在读取期间也可以使用相同的电路。

10. 发明授权

US06466481B1 Device and method for programming nonvolatile memory cells with automatic generation of programming voltage 有权
标题翻译：用于自动生成编程电压来编程非易失性存储单元的装置和方法
公开(公告)号：US06466481B1
公开(公告)日：2002-10-15
申请号：US09438232
申请日：1999-11-12
申请人： Marco Pasotti , Roberto Canegallo , Giovanni Guaitini , Pier Luigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Giovanni Guaitini , Pier Luigi Rolandi
IPC分类号： G11C1606
CPC分类号： G11C16/12
摘要： The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.
摘要翻译：该器件包括电流镜电路，其具有分别连接到待编程的存储器单元的恒定电流源和漏极端子的第一和第二节点。电压产生电路连接到第一节点以将其以恒定的参考电压（VR）偏置; 运算放大器具有连接到第一节点的反相输入端，连接到第二节点的非反相输入端，以及连接到存储器单元的控制端子的输出端。因此，存储单元的漏极端子被偏置在具有足以编程的值的恒定参考电压，并且运算放大器和存储单元形成负反馈回路，其在存储单元的控制端上提供导致存储单元写入的斜坡电压（VPCX）。斜坡电压以与阈值电压相同的速度增加，因此可以用于知道什么时候达到期望的阈值，并且因此当必须停止编程时。在第二节点和存储器单元之间存在偏置晶体管，在读取期间也可以使用相同的电路。

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