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1. 发明申请

US20080313339A1 CONNECTION MANAGEMENT METHOD, SYSTEM, AND PROGRAM PRODUCT 失效
标题翻译：连接管理方法，系统和程序产品
公开(公告)号：US20080313339A1
公开(公告)日：2008-12-18
申请号：US12191336
申请日：2008-08-14
申请人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
发明人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F12/0875 , G06F12/122 , H04L49/90 , H04L67/14 , H04L69/28
摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.
摘要翻译：本发明提供了一种用于管理连接的方法，系统和程序产品。特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

2. 发明授权

US08244880B2 Connection management method, system, and program product 失效
标题翻译：连接管理方法，系统和程序产品
公开(公告)号：US08244880B2
公开(公告)日：2012-08-14
申请号：US12191336
申请日：2008-08-14
申请人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
发明人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F12/0875 , G06F12/122 , H04L49/90 , H04L67/14 , H04L69/28
摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.
摘要翻译：本发明提供了一种用于管理连接的方法，系统和程序产品。特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

3. 发明授权

US07882302B2 Method and system for implementing prioritized refresh of DRAM based cache 失效
标题翻译：用于实现基于DRAM的缓存优先刷新的方法和系统
公开(公告)号：US07882302B2
公开(公告)日：2011-02-01
申请号：US11949859
申请日：2007-12-04
申请人： Marc R. Faucher , Peter A. Sandon , Arnold S. Tran
发明人： Marc R. Faucher , Peter A. Sandon , Arnold S. Tran
IPC分类号： G06F13/00
CPC分类号： G06F12/0893 , Y02D10/13
摘要： A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.
摘要翻译：一种用于实现多路优先刷新的方法，设置关联DRAM基高速缓存包括为多个高速缓存集中的每一个识别在当前评估周期期间未被访问的最近使用的方式的存在; 并且对于每个集合，仅刷新在当前评估期间未被访问的集合中最近识别的最近使用的方式，同时忽略该集合的剩余方式; 其中在当前评估期间对其中最近使用的最新方法的每个集合的完整检查构成了缓存的扫描。

4. 发明授权

US06457155B1 Method for making a memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket 失效
标题翻译：用于将存储卡适配器插入主板存储卡插座的方法，该插槽包括具有与主板存储卡插槽相同配置的存储卡接收插座
公开(公告)号：US06457155B1
公开(公告)日：2002-09-24
申请号：US09465609
申请日：1999-12-17
申请人： Timothy J. Dell , Kent A. Dramstad , Marc R. Faucher , Bruce G. Hazelzet
发明人： Timothy J. Dell , Kent A. Dramstad , Marc R. Faucher , Bruce G. Hazelzet
IPC分类号： G11C2900
CPC分类号： G11C5/02 , G06F11/10 , G11C5/04 , G11C2029/0411
摘要： A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of. a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.
摘要翻译：提供了一种存储卡适配器和方法，其可以向计算机系统的存储器模块添加功能或提供功能，而无需更换和丢弃现有的存储器模块。提供了一种适配器，其具有能够插入到存储器模块接收插座中的电触点。主板和存储模块接收插座，能够接收和保持诸如SIMM的存储器模块。该适配器具有逻辑，电路和/或存储器芯片，以便为现有存储器模块增加新功能，并且还具有与计算机系统的主板正确接口所需的所有信息和硬件。本发明可以在SIMM上添加诸如奇偶校验，纠错码和纠错码的各种功能，以及从系统中形成的用于在SIMM上使用的信号的转换信号，其中由计算机生成的形式的信号与 SIMM。

5. 发明授权

US5459842A System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory 失效
标题翻译：用于通过缓冲区组合来自多个CPU写请求的数据并使用读 - 修改 - 写操作将组合数据写入存储器的系统
公开(公告)号：US5459842A
公开(公告)日：1995-10-17
申请号：US905259
申请日：1992-06-26
申请人： Ralph M. Begun , Paul W. Browne , Marc R. Faucher , Gerald L. Frank , Christopher M. Herring
发明人： Ralph M. Begun , Paul W. Browne , Marc R. Faucher , Gerald L. Frank , Christopher M. Herring
IPC分类号： G06F12/00 , B82B1/00 , G06F9/38 , G06F12/04 , G06F13/16 , G06F13/38 , G06F13/14
CPC分类号： G06F13/1631
摘要： A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.
摘要翻译：写压缩缓冲器连接到CPU总线和存储器控制器以提供写周期压缩，其中对相同存储器地址的多个部分写请求被压缩为单个存储器写周期。缓冲器具有多个缓冲级别。

6. 发明申请

US20090144503A1 METHOD AND SYSTEM FOR INTEGRATING SRAM AND DRAM ARCHITECTURE IN SET ASSOCIATIVE CACHE 失效
标题翻译：用于集成缓存中的SRAM和DRAM架构的方法和系统
公开(公告)号：US20090144503A1
公开(公告)日：2009-06-04
申请号：US11949935
申请日：2007-12-04
申请人： Marc R. Faucher , Hillery C. Hunter , William R. Reohr , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： Marc R. Faucher , Hillery C. Hunter , William R. Reohr , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/123
摘要： A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.
摘要翻译：一种将混合体系结构集成在具有第一类型的存储器结构的集合关联高速缓存中的方法，所述第一类型的存储器结构用于每个同余类中的一种或多种方式，以及用于所述一致类的剩余方式的第二类型的存储器结构，包括确定存储器访问请求导致缓存命中或缓存未命中; 在高速缓存未命中的情况下，确定第一类型存储器结构的LRU方式是否也是整个同余类的LRU方式，如果不是，则将第一类型存储器结构的LRU方式的内容复制到LRU中并且在缓存未命中的情况下用新的高速缓存行填充第一类型存储器结构的LRU方式; 并根据存储器访问请求的结果更新LRU位。

7. 发明授权

US06532520B1 Method and apparatus for allocating data and instructions within a shared cache 失效
标题翻译：用于在共享缓存内分配数据和指令的方法和装置
公开(公告)号：US06532520B1
公开(公告)日：2003-03-11
申请号：US09394965
申请日：1999-09-10
申请人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
发明人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F12/127 , G06F2212/1021 , G06F2212/6042
摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.
摘要翻译：提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态第一预定计数。耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

8. 发明授权

US6108730A Memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket 失效
标题翻译：存储卡适配器可插入到主板存储卡插槽中，其包括具有与主板存储卡插槽相同配置的存储卡接收插座
公开(公告)号：US6108730A
公开(公告)日：2000-08-22
申请号：US32448
申请日：1998-02-27
申请人： Timothy J. Dell , Kent A. Dramstad , Marc R. Faucher , Bruce G. Hazelzet
发明人： Timothy J. Dell , Kent A. Dramstad , Marc R. Faucher , Bruce G. Hazelzet
IPC分类号： G06F13/14 , G11C29/00
CPC分类号： G06F13/14 , G06F11/10 , G11C5/02 , G11C2029/0411 , G11C5/04
摘要： A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.
摘要翻译：提供了一种存储卡适配器和方法，其可以向计算机系统的存储器模块添加功能或提供功能，而无需更换和丢弃现有的存储器模块。提供了一种适配器，其具有能够插入主板的存储器模块接收插座的电触点和能够接收和保持诸如SIMM的存储器模块的存储器模块接收插座。该适配器具有逻辑，电路和/或存储器芯片，以便为现有存储器模块增加新功能，并且还具有与计算机系统的主板正确接口所需的所有信息和硬件。本发明可以在SIMM上添加诸如奇偶校验，纠错码和纠错码的各种功能，以及从系统中形成的用于在SIMM上使用的信号，由计算机生成的形式的信号不兼容 SIMM。

9. 发明授权

US08019970B2 Three-dimensional networking design structure 有权
标题翻译：三维网络设计结构
公开(公告)号：US08019970B2
公开(公告)日：2011-09-13
申请号：US11946422
申请日：2007-11-28
申请人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
发明人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
IPC分类号： G06F9/00
CPC分类号： H04L41/145
摘要： A design structure embodied in a machine readable medium used in a design process includes a multi-layer silicon stack architecture having one or more processing layers comprised of one or more computing elements; one or more networking layers disposed between the processing layers, the network layer comprised of one or more networking elements, wherein each computing element comprises a plurality of network connections to adjacently disposed networking elements and each networking element may provide network access to a plurality of other computing elements through a single hop of the network.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括具有由一个或多个计算元件组成的一个或多个处理层的多层硅堆叠架构; 布置在处理层之间的一个或多个网络层，网络层由一个或多个网络元件组成，其中每个计算元件包括多个网络连接到相邻布置的联网元件，并且每个网络元件可以提供对多个其他网络的网络访问通过网络的单跳计算元素。

10. 发明授权

US07962695B2 Method and system for integrating SRAM and DRAM architecture in set associative cache 失效
标题翻译： SRAM和DRAM架构在集合关联缓存中的集成方法和系统
公开(公告)号：US07962695B2
公开(公告)日：2011-06-14
申请号：US11949935
申请日：2007-12-04
申请人： Marc R. Faucher , Hillery C. Hunter , William R. Reohr , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： Marc R. Faucher , Hillery C. Hunter , William R. Reohr , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/123
摘要： A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.
摘要翻译：一种将混合体系结构集成在具有第一类型的存储器结构的集合关联高速缓存中的方法，所述第一类型的存储器结构用于每个同余类中的一种或多种方式，以及用于所述一致类的剩余方式的第二类型的存储器结构，包括确定存储器访问请求导致缓存命中或缓存未命中; 在高速缓存未命中的情况下，确定第一类型存储器结构的LRU方式是否也是整个同余类的LRU方式，如果不是，则将第一类型存储器结构的LRU方式的内容复制到LRU中并且在缓存未命中的情况下用新的高速缓存行填充第一类型存储器结构的LRU方式; 并根据存储器访问请求的结果更新LRU位。

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