专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050282351A1 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权
标题翻译：用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统
公开(公告)号：US20050282351A1
公开(公告)日：2005-12-22
申请号：US10874038
申请日：2004-06-22
申请人： Manuel Quevedo-Lopez , James Chambers , Leif Olsen
发明人： Manuel Quevedo-Lopez , James Chambers , Leif Olsen
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
摘要翻译：本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。

2. 发明申请

US20070134886A1 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权
标题翻译：用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统
公开(公告)号：US20070134886A1
公开(公告)日：2007-06-14
申请号：US11678107
申请日：2007-02-23
申请人： Manuel Quevedo-Lopez , James Chambers , Leif Olsen
发明人： Manuel Quevedo-Lopez , James Chambers , Leif Olsen
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
摘要翻译：本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。

3. 发明申请

US20060121744A1 Top surface roughness reduction of high-k dielectric materials using plasma based processes 审中-公开
公开(公告)号：US20060121744A1
公开(公告)日：2006-06-08
申请号：US11325823
申请日：2006-01-05
申请人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
发明人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/31 , H01L21/8242
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.

4. 发明申请

US20050124109A1 Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权
标题翻译：使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低
公开(公告)号：US20050124109A1
公开(公告)日：2005-06-09
申请号：US10726987
申请日：2003-12-03
申请人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
发明人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： C23C16/40 , C23C16/56 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/302 , H01L21/461 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译：具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。

5. 发明申请

US20100008190A1 Apparatus and Method for Data Transmission from a Rotating Control Device 有权
标题翻译：用于从旋转控制装置进行数据传输的装置和方法
公开(公告)号：US20100008190A1
公开(公告)日：2010-01-14
申请号：US12500566
申请日：2009-07-09
申请人： Kevin L. Gray , Thomas F. Bailey , James Chambers
发明人： Kevin L. Gray , Thomas F. Bailey , James Chambers
IPC分类号： E21B47/18
CPC分类号： E21B33/085 , E21B3/02 , E21B7/12 , E21B17/01 , E21B21/08 , E21B33/064 , E21B47/00 , E21B47/06 , E21B47/065 , E21B47/12 , E21B47/122 , G01V11/002
摘要： The present invention generally relates to an apparatus and a method of transmitting data from a rotating control device. In one aspect, a method of transmitting data from a rotating control device coupled to an offshore drilling unit is provided. The method includes the step of generating data relating to a parameter associated with the rotating control device. The method further includes the step of transmitting the data from a transmitting assembly coupled to the rotating control device to a receiving assembly positioned proximate the transmitting assembly. Additionally, the method includes the step of transmitting the data from the receiving assembly to the offshore drilling unit. In another aspect, a data gathering and transmitting system for use with a rotating control device coupled to an offshore drilling unit is provided. In a further aspect, a method for transmitting data generated in a rotating control device coupled to a riser is provided.
摘要翻译：本发明一般涉及从旋转控制装置发送数据的装置和方法。一方面，提供一种从耦合到海上钻井单元的旋转控制装置传送数据的方法。该方法包括生成与旋转控制装置相关的参数有关的数据的步骤。该方法还包括将数据从耦合到旋转控制装置的发送组件传送到靠近发射组件定位的接收组件的步骤。此外，该方法包括将数据从接收组件传送到海上钻井单元的步骤。在另一方面，提供了一种与耦合到海上钻井单元的旋转控制装置一起使用的数据收集和传送系统。在另一方面，提供一种用于传送在连接到提升管的旋转控制装置中产生的数据的方法。

6. 发明申请

US20080068926A1 UNDERWATER BIOMASS ASSESSMENT DEVICE AND METHOD 有权
标题翻译：水下生物量评估装置和方法
公开(公告)号：US20080068926A1
公开(公告)日：2008-03-20
申请号：US11691481
申请日：2007-03-26
申请人： James Chambers , Henry Bass , Kenneth Gilbert , Daniel Kleinert
发明人： James Chambers , Henry Bass , Kenneth Gilbert , Daniel Kleinert
IPC分类号： G01S15/88 , G03B42/06
CPC分类号： G03B42/06 , G01S15/96
摘要： A system for assessing underwater biomass that comprises a frame that can float and hold the system on a body of water; a transducer that emits and receives wave signals; a motor box, that positions the transducer below a water line; a control unit to allow a user to operate the system and view results obtained from the system; an electronics housing that receives a CPU board that communicates with and relays information to and from, the control unit; and a communication device to facilitate communication between the control unit and the CPU board.
摘要翻译：一种用于评估水下生物质的系统，包括可将系统浮动并保持在水体上的框架; 发射和接收波信号的换能器; 电机箱，将换能器放置在水线下方; 控制单元，用于允许用户操作系统并查看从系统获得的结果; 电子外壳，其接收与控制单元通信和中继信息的CPU板; 以及促进控制单元和CPU板之间的通信的通信设备。

7. 发明申请

US20080057739A1 Defect Control in Gate Dielectrics 有权
标题翻译：门电介质中的缺陷控制
公开(公告)号：US20080057739A1
公开(公告)日：2008-03-06
申请号：US11924132
申请日：2007-10-25
申请人： Luigi Colombo , James Chambers , Mark Visokay , Antonio Rotondaro
发明人： Luigi Colombo , James Chambers , Mark Visokay , Antonio Rotondaro
IPC分类号： H01L21/469
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

8. 发明申请

US20050258500A1 Refractory metal-based electrodes for work function setting in semiconductor devices 有权
$Refractory metal-based electrodes for work function setting in semiconductor devices$
标题翻译：用于半导体器件功能设置的耐火金属基电极
公开(公告)号：US20050258500A1
公开(公告)日：2005-11-24
申请号：US10852523
申请日：2004-05-24
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/3205 , H01L21/8234 , H01L21/8238 , H01L29/49 , H01L29/76 , H01L29/78
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译：本发明在一个实施例中提供一种栅极结构（100）。栅极结构包括栅极电介质（105）和栅极（110）。栅极电介质包括难熔金属并且位于半导体衬底（115）之上。半导体衬底具有导带和价带。栅极位于栅极电介质上方并且包括难熔金属。栅极具有与导带或价带对准的功函数。其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

9. 发明申请

US20050258468A1 Dual work function metal gate integration in semiconductor devices 有权
标题翻译：双功能金属门集成在半导体器件中
公开(公告)号：US20050258468A1
公开(公告)日：2005-11-24
申请号：US10890365
申请日：2004-07-13
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/3205 , H01L21/8234 , H01L21/8238 , H01L29/49 , H01L29/76 , H01L29/78
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
摘要翻译：本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。金属层的功函数与半导体衬底的导带或价带相匹配。该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。

10. 发明申请

US20050059198A1 Metal gate MOS transistors and methods for making the same 有权
标题翻译：金属栅极MOS晶体管及其制造方法
公开(公告)号：US20050059198A1
公开(公告)日：2005-03-17
申请号：US10661130
申请日：2003-09-12
申请人： Mark Visokay , Luigi Colombo , James Chambers
发明人： Mark Visokay , Luigi Colombo , James Chambers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/44 , H01L29/76
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/513 , H01L29/517 , H01L29/665
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.
摘要翻译：提供了半导体器件和制造方法，其中为MOS晶体管提供金属晶体管栅极。金属硼化物形成在栅极电介质上方以产生PMOS栅极结构，并且在栅极电介质上形成金属氮化物以提供NMOS栅极结构。栅极结构的金属部分由起始原料是金属硼化物或金属氮化物形成，之后起始材料通过注入，扩散或扩散形成在PMOS和NMOS区域之一中的硼或氮中。在形成导电上部材料之前或之后以及栅极图案化之前或之后的其它技术。起始材料的硼或氮含量的变化提供材料功函数的调整，从而调谐所得PMOS或NMOS晶体管的阈值电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式