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1. 发明申请

US20060024910A1 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
标题翻译：在CMOS技术中使用浅沟槽隔离（STI）来设计反向窄宽度效应（INWE）的方法，
公开(公告)号：US20060024910A1
公开(公告)日：2006-02-02
申请号：US10899664
申请日：2004-07-27
申请人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
发明人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).
摘要翻译：公开了一种形成隔离结构的方法（200），并且包括在与隔离区域相关联的半导体本体（214）中形成隔离沟槽，并用植入物掩模材料（216）填充隔离沟槽的底部。在其底部填充有注入掩模材料之后，在隔离沟槽（218）中进行成角度的离子注入，从而在半导体本体中形成阈值电压补偿区域。随后，隔离沟槽填充有电介质材料（220）。

2. 发明授权

US08008216B2 Nitrogen profile in high-K dielectrics using ultrathin disposable capping layers 有权
标题翻译：使用超薄一次性封盖层的高K电介质中的氮分布
公开(公告)号：US08008216B2
公开(公告)日：2011-08-30
申请号：US11860066
申请日：2007-09-24
申请人： Husam Alshareef , Manuel Quevedo Lopez
发明人： Husam Alshareef , Manuel Quevedo Lopez
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28238 , H01L21/28202 , H01L21/823857 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric—transistor substrate interface.
摘要翻译：使用现有技术制造的金属氧化物半导体（MOS）晶体管可以利用栅极电介质上的氮化工艺来提高晶体管的可靠性。目前的技术的氮化，其涉及将栅极电介质暴露于氮化源，在栅极电介质和晶体管衬底的界面处产生显着的氮浓度，这对晶体管性能产生不利影响。本发明包括在氮化之前在栅极电介质上沉积牺牲层的过程，将牺牲层暴露于氮化源，在此期间氮原子通过牺牲层扩散到栅极电介质中，然后去除牺牲层而不降低栅电介质。与本发明相关的高k栅极电介质的工作已经证明了在栅极介电晶体管衬底界面处的氮浓度降低了20％。

3. 发明申请

US20050124109A1 Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权
标题翻译：使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低
公开(公告)号：US20050124109A1
公开(公告)日：2005-06-09
申请号：US10726987
申请日：2003-12-03
申请人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
发明人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： C23C16/40 , C23C16/56 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/302 , H01L21/461 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译：具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。

4. 发明申请

US20090104743A1 Nitrogen Profile in High-K Dielectrics Using Ultrathin Disposable Capping Layers 有权
标题翻译：使用超薄一次性封盖层的高K电介质中的氮分布
公开(公告)号：US20090104743A1
公开(公告)日：2009-04-23
申请号：US11860066
申请日：2007-09-24
申请人： Husam Alshareef , Manuel Quevedo Lopez
发明人： Husam Alshareef , Manuel Quevedo Lopez
IPC分类号： H01L21/8238 , H01L21/3115
CPC分类号： H01L21/28238 , H01L21/28202 , H01L21/823857 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric-transistor substrate interface.
摘要翻译：使用现有技术制造的金属氧化物半导体（MOS）晶体管可以利用栅极电介质上的氮化工艺来提高晶体管的可靠性。目前的技术的氮化，其涉及将栅极电介质暴露于氮化源，在栅极电介质和晶体管衬底的界面处产生显着的氮浓度，这对晶体管性能产生不利影响。本发明包括在氮化之前在栅极电介质上沉积牺牲层的过程，将牺牲层暴露于氮化源，在此期间氮原子通过牺牲层扩散到栅极电介质中，然后去除牺牲层而不降低栅电介质。与本发明相关的高k栅极电介质的工作已经证明了在栅极介电晶体管衬底界面处的氮浓度降低了20％。

5. 发明授权

US07199021B2 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权
公开(公告)号：US07199021B2
公开(公告)日：2007-04-03
申请号：US10874038
申请日：2004-06-22
申请人： Manuel Quevedo-Lopez , James J. Chambers , Leif Christian Olsen
发明人： Manuel Quevedo-Lopez , James J. Chambers , Leif Christian Olsen
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

6. 发明申请

US20060121744A1 Top surface roughness reduction of high-k dielectric materials using plasma based processes 审中-公开
公开(公告)号：US20060121744A1
公开(公告)日：2006-06-08
申请号：US11325823
申请日：2006-01-05
申请人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
发明人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/31 , H01L21/8242
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.

7. 发明授权

US07045436B2 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
公开(公告)号：US07045436B2
公开(公告)日：2006-05-16
申请号：US10899664
申请日：2004-07-27
申请人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
发明人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
IPC分类号： H01L21/762
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

8. 发明申请

US20050282351A1 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权
标题翻译：用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统
公开(公告)号：US20050282351A1
公开(公告)日：2005-12-22
申请号：US10874038
申请日：2004-06-22
申请人： Manuel Quevedo-Lopez , James Chambers , Leif Olsen
发明人： Manuel Quevedo-Lopez , James Chambers , Leif Olsen
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
摘要翻译：本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。

9. 发明申请

US20080242114A1 THERMAL ANNEAL METHOD FOR A HIGH-K DIELECTRIC 审中-公开
标题翻译：用于高K电介质的热绝缘方法
公开(公告)号：US20080242114A1
公开(公告)日：2008-10-02
申请号：US11695324
申请日：2007-04-02
申请人： Manuel Quevedo-Lopez , Husam Alshareef
发明人： Manuel Quevedo-Lopez , Husam Alshareef
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a semiconductor device is provided. In one embodiment, the method provides for the formation, over a substrate, of a dielectric layer having a high dielectric constant. This dielectric layer may be exposed to a nitrogen plasma after which it may be annealed in a hydrogen containing ambient.
摘要翻译：提供一种制造半导体器件的方法。在一个实施例中，该方法提供了在衬底上形成具有高介电常数的电介质层。该介电层可以暴露于氮等离子体之后，其可以在含氢环境中进行退火。

10. 发明申请

US20080237604A1 PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE 审中-公开
标题翻译：等离子体氮化物氧化物，高K金属栅基CMOS器件
公开(公告)号：US20080237604A1
公开(公告)日：2008-10-02
申请号：US11694419
申请日：2007-03-30
申请人： Husam Niman Alshareef , Manuel Quevedo-Lopez
发明人： Husam Niman Alshareef , Manuel Quevedo-Lopez
IPC分类号： H01L27/108 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/02164 , H01L21/02181 , H01L21/02189 , H01L21/02332 , H01L21/0234 , H01L21/28194 , H01L21/28202 , H01L21/3145 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/823828 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer.
摘要翻译：根据本发明，存在CMOS器件和半导体器件及其制造方法。 CMOS器件可以包括在第一有源区上方包括第一有源区和第二有源区的衬底和第一晶体管器件，其中第一晶体管器件包括在第一有源区上的高K层，第一介电覆盖层在高K层上，以及在第一介电覆盖层上方的第一金属栅极层。 CMOS器件还可以包括在第二有源区上的第二晶体管器件，其中第二晶体管器件包括在第二有源区上的高K层，在第二高K层上的第二介电覆盖层，以及第二金属栅极层在第二介电覆盖层上。

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