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1. 发明授权

US08450832B2 Large tuning range junction varactor 有权
标题翻译：大调谐范围结变容二极管
公开(公告)号：US08450832B2
公开(公告)日：2013-05-28
申请号：US11696732
申请日：2007-04-05
申请人： Manju Sarkar , Purakh Raj Verma
发明人： Manju Sarkar , Purakh Raj Verma
IPC分类号： H01L29/93
CPC分类号： H01L27/0808 , H01L29/93
摘要： Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.
摘要翻译：大型调谐范围结变容二极管包括并联在第一和第二变容二极管端子之间的第一和第二结电容器。电容器的第一和第二板由衬底中的三个交替掺杂区域形成。第一和第三掺杂区域具有夹着第二类型的第二掺杂区域的相同类型。第一输入端子耦合到第一和第三掺杂区域，第二端子耦合到第二掺杂区域。在掺杂区域的界面处是第一和第二耗尽区域，其宽度可以通过将端子间的电压从零改变为全反向偏压来改变。

2. 发明申请

US20080246071A1 MOS VARACTORS WITH LARGE TUNING RANGE 有权
标题翻译：具有大调谐范围的MOS变送器
公开(公告)号：US20080246071A1
公开(公告)日：2008-10-09
申请号：US11696736
申请日：2007-04-05
申请人： Manju Sarkar , Purakh Raj Verma
发明人： Manju Sarkar , Purakh Raj Verma
IPC分类号： H01L29/94 , H01L21/334 , H01L31/00
CPC分类号： H01L29/93 , H01L29/66189 , H01L29/94
摘要： A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.
摘要翻译： MOS变容二极管包括在MOS结构的衬底的表面下面的浅PN结。在耗尽模式中，MOS结构的耗尽区与浅PN结的耗尽区相结合。这增加了MOS变容二极管的耗尽区的总宽度以减少C min min。

3. 发明授权

US07994563B2 MOS varactors with large tuning range 有权
标题翻译：具有较大调谐范围的MOS变容二极管
公开(公告)号：US07994563B2
公开(公告)日：2011-08-09
申请号：US12616150
申请日：2009-11-11
申请人： Manju Sarkar , Purakh Raj Verma
发明人： Manju Sarkar , Purakh Raj Verma
IPC分类号： H01L27/108 , H01L29/93
CPC分类号： H01L29/93 , H01L29/66189 , H01L29/94
摘要： A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device. In depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction.
摘要翻译：提供了一个设备。该装置包括具有第一极性类型的第一阱的衬底。第一阱限定变容二极管区域并且包括位于衬底的底表面上方的下第一阱边界。变容二极管区域中的第二个井也包含在设备中。第二井包括具有第二极性类型的埋井，其具有设置在第一井的上部下方的上第二井边界，从上第一井边界到上第二井边界，以及设置在下第一井边界的下第二井边界其中第二阱的界面和第一阱的上部在变容二极管区域中形成浅PN结。该装置还包括变容二极管区域中的栅极结构。栅极结构下面的第一阱的上部形成器件的沟道区。在耗尽模式中，沟道区域中的栅极结构之下的耗尽区域与浅PN结的耗尽区域合并。

4. 发明授权

US06372652B1 Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage 有权
标题翻译：用可重现的吹制瓦数形成薄膜可电熔熔断器的方法
公开(公告)号：US06372652B1
公开(公告)日：2002-04-16
申请号：US09494633
申请日：2000-01-31
申请人： Purakh Raj Verma , Zia Alan Shafi , Yu Shan , Zeng Zheng , Manju Sarkar , Shao-Fu Sanford Chu
发明人： Purakh Raj Verma , Zia Alan Shafi , Yu Shan , Zeng Zheng , Manju Sarkar , Shao-Fu Sanford Chu
IPC分类号： H01L21302
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.
摘要翻译：一种用于在熔丝电介质层和两个蚀刻工艺上使用牺牲金属贴片形成具有可再现的吹扫功率的薄膜电可熔电熔丝的方法; 其中所述第一蚀刻工艺对所述金属贴片是选择性的，并且所述第二蚀刻工艺对所述熔丝电介质层是选择性的。在半导体结构上形成具有元件宽度的熔丝元件，并且在保险丝元件上形成熔丝电介质层。在熔丝绝缘层上形成牺牲金属贴片; 其中所述贴片宽度大于所述熔丝元件宽度。在牺牲金属贴片上形成第二电介质层，并且可以在第二电介质层上形成附加的金属层和电介质层，但是只有电介质层将保留在熔丝元件上方。使用对牺牲金属贴片选择性的第一熔丝窗口蚀刻，将第二电介质层和任何上覆电介质层图案化以形成具有大于牺牲金属贴片的宽度的熔丝窗口。然后，使用对熔丝电介质层选择性的第二熔丝窗蚀刻，通过熔丝窗口蚀刻牺牲金属贴片，留下覆于熔丝元件上的熔丝电介质层的可再现厚度; 从而提供可重复的吹制瓦数。

5. 发明授权

US07618873B2 MOS varactors with large tuning range 有权
标题翻译：具有较大调谐范围的MOS变容二极管
公开(公告)号：US07618873B2
公开(公告)日：2009-11-17
申请号：US11696736
申请日：2007-04-05
申请人： Manju Sarkar , Purakh Raj Verma
发明人： Manju Sarkar , Purakh Raj Verma
IPC分类号： H01L21/20 , H01L21/425
CPC分类号： H01L29/93 , H01L29/66189 , H01L29/94
摘要： A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.
摘要翻译： MOS变容二极管包括在MOS结构的衬底的表面下面的浅PN结。在耗尽模式中，MOS结构的耗尽区与浅PN结的耗尽区相结合。这增加了MOS变容二极管的耗尽区域的总宽度以减小Cmin。

6. 发明申请

US20080246119A1 LARGE TUNING RANGE JUNCTION VARACTOR 有权
标题翻译：大型调谐范围变送器
公开(公告)号：US20080246119A1
公开(公告)日：2008-10-09
申请号：US11696732
申请日：2007-04-05
申请人： Manju SARKAR , Purakh Raj Verma
发明人： Manju SARKAR , Purakh Raj Verma
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L27/0808 , H01L29/93
摘要： Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.
摘要翻译：大型调谐范围结变容二极管包括并联在第一和第二变容二极管端子之间的第一和第二结电容器。电容器的第一和第二板由衬底中的三个交替掺杂区域形成。第一和第三掺杂区域具有夹着第二类型的第二掺杂区域的相同类型。第一输入端子耦合到第一和第三掺杂区域，第二端子耦合到第二掺杂区域。在掺杂区域的界面处是第一和第二耗尽区域，其宽度可以通过将端子间的电压从零改变为全反向偏压来改变。

7. 发明授权

US08802484B1 Integration of germanium photo detector in CMOS processing 有权
标题翻译：锗光电检测器在CMOS处理中的集成
公开(公告)号：US08802484B1
公开(公告)日：2014-08-12
申请号：US13747009
申请日：2013-01-22
申请人： Purakh Raj Verma , Guowei Zhang , Kah Wee Ang
发明人： Purakh Raj Verma , Guowei Zhang , Kah Wee Ang
IPC分类号： H01L21/00 , H01L31/102
CPC分类号： H01L21/02532 , H01L21/84 , H01L27/0617 , H01L27/1203 , H01L31/028
摘要： A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.
摘要翻译：提供了一种通过Ge或Ge / Si的非选择性外延生长在CMOS工艺中形成集成的Ge或Ge / Si光电检测器的方法和装置。实施例包括在Si衬底中形成N阱; 在Si衬底中形成晶体管或电阻器; 在Si衬底和晶体管或电阻器上形成ILD; 在ILD上形成Si基电介质层; 在所述Si基电介质层上形成多晶硅或Si-Si层; 在多晶硅或a-Si层中形成沟槽，Si基介电层，ILD和N阱; 在沟槽中形成Ge或Ge / Si; 并且将Ge或Ge / Si，多晶硅或a-Si层以及Si基介电层除去到ILD的上表面。另外的方面包括在Ge或Ge / Si上形成原位掺杂的Si帽外延层或非原位掺杂的多晶Si或者a-Si覆盖层。

8. 发明授权

US08645876B2 Methodology for performing post layer generation check 有权
标题翻译：执行后期生成检查的方法
公开(公告)号：US08645876B2
公开(公告)日：2014-02-04
申请号：US13234117
申请日：2011-09-15
申请人： Wye Boon Loh , Jeoung Mo Koo , Paul Kim Cheong Soh , Beng Lye Oh , Purakh Raj Verma
发明人： Wye Boon Loh , Jeoung Mo Koo , Paul Kim Cheong Soh , Beng Lye Oh , Purakh Raj Verma
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.
摘要翻译：提供了一种方法，包括接收对应于多个输入掩模层的布局设计的数据，并且生成用于至少一个生成的掩模层的布局设计。然后确定并验证包括生成的掩模层中的一个或多个的第一布局图案中的第一几何元素与第二布局图案中的第二几何元素之间的关系，以检查它们是否符合预定规则。如果关系不符合预定规则，则修改与第一或第二布局图案相关联的所生成的掩模层中的至少一个的设计。

9. 发明授权

US08507983B2 High voltage device 有权
标题翻译：高压设备
公开(公告)号：US08507983B2
公开(公告)日：2013-08-13
申请号：US13550571
申请日：2012-07-16
申请人： Guowei Zhang , Purakh Raj Verma
发明人： Guowei Zhang , Purakh Raj Verma
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/823807 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.
摘要翻译：公开了一种设备。该器件包括用有源器件区域制备的衬底。有源器件区域包括栅极。该器件还包括在栅极的第一边缘附近设置在衬底中的掺杂沟道。栅极的第一边缘与沟道的沟道边缘很好地与沟道的沟道边缘重叠。栅极和沟道边缘的第一个边缘定义了器件的有效沟道长度。有效通道长度与栅极自对准。还包括与栅极的第二边缘相邻的掺杂漂移阱。

10. 发明授权

US08410553B2 Semiconductor structure including high voltage device 有权
标题翻译：半导体结构包括高压器件
公开(公告)号：US08410553B2
公开(公告)日：2013-04-02
申请号：US12964753
申请日：2010-12-10
申请人： Jeoung Mo Koo , Purakh Raj Verma , Sanford Chu , Chunlin Zhu , Yisuo Li
发明人： Jeoung Mo Koo , Purakh Raj Verma , Sanford Chu , Chunlin Zhu , Yisuo Li
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/105 , H01L29/66568 , H01L29/7833
摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.
摘要翻译：高压器件包括其上限定有器件区域的衬底。栅极堆叠设置在器件区域中的衬底上。沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

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