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1. 发明申请

US20060024873A1 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US20060024873A1
公开(公告)日：2006-02-02
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

2. 发明申请

US20050118770A1 Method for introducing hydrogen into a channel region of a metal oxide semiconductor (MOS) device 审中-公开
标题翻译：将氢引入金属氧化物半导体（MOS）器件的沟道区域的方法
公开(公告)号：US20050118770A1
公开(公告)日：2005-06-02
申请号：US10956864
申请日：2004-10-01
申请人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
发明人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
IPC分类号： H01L21/30 , H01L21/324 , H01L21/336 , H01L29/78 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/3003 , H01L21/324 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (230) over a substrate (210) and forming at least a portion of source/drain regions in the substrate (210). The method further includes annealing the substrate containing the at least a portion of source/drain regions in the presence of hydrogen, and forming an interlevel dielectric layer over the substrate (210) having previously been annealed in the presence of hydrogen.
摘要翻译：本发明提供一种半导体器件的制造方法及其制造方法。除了其他步骤之外，制造半导体器件的方法包括在衬底（210）上形成栅极结构（230）并且形成衬底（210）中的源极/漏极区域的至少一部分。该方法还包括在存在氢的情况下对包含至少一部分源极/漏极区的衬底进行退火，以及在预先在氢气存在下预先退火的衬底（210）上形成层间电介质层。

3. 发明授权

US08101476B2 Stress memorization dielectric optimized for NMOS and PMOS 有权
标题翻译：针对NMOS和PMOS优化的应力记忆电介质
公开(公告)号：US08101476B2
公开(公告)日：2012-01-24
申请号：US12541335
申请日：2009-08-14
申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
发明人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
摘要翻译：一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

4. 发明授权

US07402535B2 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US07402535B2
公开(公告)日：2008-07-22
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

5. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

6. 发明申请

US20090166675A1 STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体器件中的应变工程
公开(公告)号：US20090166675A1
公开(公告)日：2009-07-02
申请号：US12346458
申请日：2008-12-30
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L29/737 , H01L21/265 , H01L21/337
CPC分类号： H01L21/02658 , H01L21/02667
摘要： This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.
摘要翻译：本公开涉及应变工程，以改善包括半导体衬底的应变区域的半导体部件的性能。本公开涉及目标区域的非晶化和原子格子的再结晶，同时在该区域上施加应变。这样形成的区域将形成应变格子，其中应变均匀地分布在整个区域中，并且即使去除了机械应变源，其也保留了本征应变。本公开包括用于形成具有应变区域（例如具有应变通道区域的半导体部件）和由其形成的半导体部件的半导体衬底的方法以及具有各种性质和优点的变型。

7. 发明申请

US20090004805A1 Damage Implantation of a Cap Layer 有权
标题翻译：盖层的损伤植入
公开(公告)号：US20090004805A1
公开(公告)日：2009-01-01
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L23/58
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

8. 发明授权

US07393787B2 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment 有权
标题翻译：使用高温化学处理形成其中具有均匀氮分布的含氮介电层
公开(公告)号：US07393787B2
公开(公告)日：2008-07-01
申请号：US11209140
申请日：2005-08-22
申请人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
发明人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
IPC分类号： H01L21/302
CPC分类号： H01L27/11 , H01L21/823462 , H01L21/823857 , H01L21/8249
摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.
摘要翻译：本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

9. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

10. 发明授权

US07678637B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US07678637B2
公开(公告)日：2010-03-16
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

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