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1. 发明授权

US08487447B2 Semiconductor structure having offset passivation to reduce electromigration 有权
标题翻译：具有偏移钝化以减少电迁移的半导体结构
公开(公告)号：US08487447B2
公开(公告)日：2013-07-16
申请号：US13111283
申请日：2011-05-19
申请人： Mario J. Interrante , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
发明人： Mario J. Interrante , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/02163 , H01L2224/0401 , H01L2224/05147 , H01L2224/05551 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/0569 , H01L2224/06131 , H01L2224/06134 , H01L2224/13005 , H01L2224/13016 , H01L2224/13022 , H01L2224/13025 , H01L2224/13026 , H01L2224/13028 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/014 , H01L2924/15311 , H01L2924/049 , H01L2924/053 , H01L2224/05552
摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.
摘要翻译：一种半导体结构，其包括三维结构中的多个层叠半导体芯片。存在与第二半导体芯片接触的第一半导体芯片。第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移与导电垫。

2. 发明申请

US20120292779A1 SEMICONDUCTOR STRUCTURE HAVING OFFSET PASSIVATION TO REDUCE ELECTROMIGRATION 有权
标题翻译：半导体结构具有减少电磁偏移的局限性
公开(公告)号：US20120292779A1
公开(公告)日：2012-11-22
申请号：US13111283
申请日：2011-05-19
申请人： MARIO J. INTERRANTE , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
发明人： MARIO J. INTERRANTE , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/02163 , H01L2224/0401 , H01L2224/05147 , H01L2224/05551 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/0569 , H01L2224/06131 , H01L2224/06134 , H01L2224/13005 , H01L2224/13016 , H01L2224/13022 , H01L2224/13025 , H01L2224/13026 , H01L2224/13028 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/014 , H01L2924/15311 , H01L2924/049 , H01L2924/053 , H01L2224/05552
摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.
摘要翻译：一种半导体结构，其包括三维结构中的多个层叠半导体芯片。存在与第二半导体芯片接触的第一半导体芯片。第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移与导电垫。

3. 发明授权

US07545648B2 Cooling structure using rigid movable elements 失效
标题翻译：冷却结构采用刚性可动元件
公开(公告)号：US07545648B2
公开(公告)日：2009-06-09
申请号：US12055263
申请日：2008-03-25
申请人： John P. Karidis , Mark D. Schultz , Bucknell C. Webb
发明人： John P. Karidis , Mark D. Schultz , Bucknell C. Webb
IPC分类号： H05K7/20 , H01L23/34
CPC分类号： H01L23/433 , H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： An information processing system includes: a processor; a memory; an input/output subsystem; and a bus coupled to the processor, the memory and the input/output subsystem. The system further includes a cooling structure for cooling the processor. The cooling structure consists of: a compressible backing; a plurality of rigid copper elements disposed between the backing and the processor; a first conformable heat-conducting layer disposed over the processor; a second conformable heat-conducting layer disposed between the compressible backing and the rigid elements; a liquid coolant; and a seal for containing the liquid coolant.
摘要翻译：一种信息处理系统，包括：处理器; 记忆输入/输出子系统; 以及耦合到处理器，存储器和输入/输出子系统的总线。该系统还包括用于冷却处理器的冷却结构。冷却结构包括：可压缩背衬; 设置在背衬和处理器之间的多个刚性铜元件; 设置在所述处理器上的第一适形导热层; 设置在可压缩背衬和刚性元件之间的第二适形导热层; 液体冷却剂; 以及用于容纳液体冷却剂的密封件。

4. 发明授权

US5991115A Method and apparatus for determining separation between read and write elements of a transducer 失效
标题翻译：用于确定换能器的读取和写入元件之间的分离的方法和装置
公开(公告)号：US5991115A
公开(公告)日：1999-11-23
申请号：US211138
申请日：1998-12-14
申请人： Timothy Joseph Chainer , Anthony Paul Praino , Mark Delorman Schultz , Bucknell C. Webb , Edward John Yarmchuk
发明人： Timothy Joseph Chainer , Anthony Paul Praino , Mark Delorman Schultz , Bucknell C. Webb , Edward John Yarmchuk
IPC分类号： G11B5/55 , G11B5/596 , G11B19/04 , G11B21/10
CPC分类号： G11B19/04 , G11B21/106 , G11B5/5565 , G11B5/59633
摘要： Improvements in placement of timing patterns in self servo writing include correcting for random and systematic errors due to geometric effects. In a disk drive having a recording head with separate read and write elements, a method for determining separation between the elements and for correcting for such errors as a function of skew angle between the head and the disk. Errors resulting from misalignment and non-parallelism of the elements as well as misalignment of the head on it its actuator are also detected and corrected. Errors due to changes in rotational velocity of the disk and misplacement of timing patterns with respect to adjacent timing patterns are detected and corrected. In general, a single revolution process may be used to both write and detect random errors on each track and corrected on subsequent tracks.
摘要翻译：自动写入中定时模式布置的改进包括纠正由于几何效应引起的随机和系统误差。在具有具有分离的读取和写入元件的记录头的磁盘驱动器中，确定元件之间的间隔并用于校正这种错误的方法，其作为头部和盘之间的歪斜角的函数。元件的不对准和不平行度导致的误差以及头部在其致动器上的未对准性也被检测和校正。检测并纠正由于盘的旋转速度的变化引起的错误和定时图案相对于相邻的定时图案的错位。通常，可以使用单次旋转处理来写入和检测每个轨道上的随机误差并在随后的轨道上进行校正。

5. 发明授权

US10173888B2 Small wafer area MEMs switch 有权
公开(公告)号：US10173888B2
公开(公告)日：2019-01-08
申请号：US15650788
申请日：2017-07-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , Bucknell C. Webb
发明人： Bucknell C. Webb
IPC分类号： B81B3/00 , B81C1/00 , G01R33/02 , G01R33/028 , H01H51/22
摘要： Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

6. 发明申请

US20170166438A1 SMALL WAFER AREA MEMS SWITCH 有权
公开(公告)号：US20170166438A1
公开(公告)日：2017-06-15
申请号：US14969329
申请日：2015-12-15
申请人： Bucknell C. Webb
发明人： Bucknell C. Webb
IPC分类号： B81B3/00 , B81C1/00
CPC分类号： B81B3/0056 , B81B2201/012 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C1/0015 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , B81C2201/0178 , B81C2203/0109 , B81C2203/0136 , H01H59/0009 , H01H2001/0078
摘要： Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

7. 发明申请

US20140013606A1 UNDERFILL MATERIAL DISPENSING FOR STACKED SEMICONDUCTOR CHIPS 有权
标题翻译：堆叠半导体芯片的材料分配
公开(公告)号：US20140013606A1
公开(公告)日：2014-01-16
申请号：US13567567
申请日：2012-08-06
申请人： Jae-Woong Nah , Katsuyuki Sakuma , Bucknell C. Webb
发明人： Jae-Woong Nah , Katsuyuki Sakuma , Bucknell C. Webb
IPC分类号： B43L7/00
CPC分类号： H01L21/50 , H01L21/561 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06582 , H01L2224/32145 , H01L2924/00012 , H01L2224/32225 , H01L2224/81 , H01L2924/014
摘要： A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.
摘要翻译：可以使用具有锥形开口的模板，以使得能够通过具有小于底部填充材料的注射器针的横向尺寸的间隙的间隙注入底部填充材料。每个锥形开口具有在上侧上的第一横向尺寸和在下侧上的第二横向尺寸。可以采用符合材料的部分来适应模板和堆叠的半导体芯片和/或注射器头之间的距离的变化。可选地，在将底部填充材料施加到间隙之后，可以使用另一个头部来施加压缩气体以推出底部填充材料。可以使用多个注射器头来同时将底部填充材料注入不同的位置。粘合剂层可以代替至少一个下顺应材料部分。

8. 发明授权

US08492901B2 Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof 失效
标题翻译：金属氧化物半导体（MOS）兼容的高纵横比透晶片通孔及其低应力结构
公开(公告)号：US08492901B2
公开(公告)日：2013-07-23
申请号：US12614062
申请日：2009-11-06
申请人： Bucknell C. Webb
发明人： Bucknell C. Webb
IPC分类号： H01L23/538
CPC分类号： H01L23/481 , H01L21/76898 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.
摘要翻译：一种结构包括具有顶部晶片表面的晶片。晶片限定开口。顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。晶片具有第一基准方向的厚度。该结构还包括形成在开口中的贯通晶片通孔。当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。还公开了制造技术。

9. 发明授权

US08385018B2 Magnetic writer having multiple gaps with more uniform magnetic fields across the gaps 有权
标题翻译：具有多个间隙的磁记录器，跨越间隙具有更均匀的磁场
公开(公告)号：US08385018B2
公开(公告)日：2013-02-26
申请号：US12611294
申请日：2009-11-03
申请人： Robert G. Biskeborn , Philipp Herget , Bucknell C. Webb
发明人： Robert G. Biskeborn , Philipp Herget , Bucknell C. Webb
IPC分类号： G11B5/265
CPC分类号： G11B5/3116 , G11B5/17 , G11B5/23 , G11B5/265 , G11B5/2652 , G11B5/59638
摘要： A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.
摘要翻译：根据一个实施例的磁性装置包括通量源; 耦合到磁通源的磁极，所述磁极具有两个或更多个间隙; 以及朝向所述间隙中的至少一个定位的低磁阻路径，并且朝向所述间隙中的至少另一个定位，以在所述通量源产生磁通时影响形成在所述至少一个间隙处的磁场。其他公开的实施例包括具有在磁轭中具有不均匀布置的线圈匝的装置，用于在写入期间改变在至少一个间隙处形成的磁场。在另外的实施例中，靠近或在其中一个间隙处的磁极的几何形状不同于磁极在靠近或另一个间隙处的几何形状，以帮助当磁通源产生磁通时在间隙处形成的场均衡。

10. 发明申请

US20110108958A1 Metal Oxide Semiconductor (MOS)-Compatible High-Aspect Ratio Through-Wafer Vias and Low-Stress Configuration Thereof 失效
标题翻译：金属氧化物半导体（MOS） - 兼容的高宽比通过晶片通孔和低应力配置
公开(公告)号：US20110108958A1
公开(公告)日：2011-05-12
申请号：US12614062
申请日：2009-11-06
申请人： Bucknell C. Webb
发明人： Bucknell C. Webb
IPC分类号： H01L23/48 , H01L21/3205 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76898 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.
摘要翻译：一种结构包括具有顶部晶片表面的晶片。晶片限定开口。顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。晶片具有第一基准方向的厚度。该结构还包括形成在开口中的贯通晶片通孔。当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。还公开了制造技术。

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