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1. 发明授权

US08492236B1 Step-like spacer profile 有权
标题翻译：阶梯状间隔剖面
公开(公告)号：US08492236B1
公开(公告)日：2013-07-23
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

2. 发明申请

US20130181259A1 STEP-LIKE SPACER PROFILE 有权
公开(公告)号：US20130181259A1
公开(公告)日：2013-07-18
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

3. 发明授权

US08828858B2 Spacer profile engineering using films with continuously increased etch rate from inner to outer surface 有权
标题翻译：使用具有从内到外表面的不断增加的蚀刻速率的膜的间隔轮廓工程
公开(公告)号：US08828858B2
公开(公告)日：2014-09-09
申请号：US13353684
申请日：2012-01-19
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6653 , H01L29/6656
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
摘要翻译：通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

4. 发明申请

US20130187202A1 SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE 有权
标题翻译：使用膜的间隙轮廓工程，从内部到外表面连续增加的刻蚀速率
公开(公告)号：US20130187202A1
公开(公告)日：2013-07-25
申请号：US13353684
申请日：2012-01-19
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/6653 , H01L29/6656
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
摘要翻译：通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

5. 发明授权

US08940637B2 Method for forming through silicon via with wafer backside protection 有权
标题翻译：通过硅晶片背面保护形成硅通孔的方法
公开(公告)号：US08940637B2
公开(公告)日：2015-01-27
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/44 , H01L21/768 , H01L21/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

6. 发明申请

US20140008810A1 METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION 有权
标题翻译：通过硅片防止背面保护形成硅的方法
公开(公告)号：US20140008810A1
公开(公告)日：2014-01-09
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/306 , H01L23/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

7. 发明授权

US08518775B2 Integration of eNVM, RMG, and HKMG modules 有权
标题翻译：集成eNVM，RMG和HKMG模块
公开(公告)号：US08518775B2
公开(公告)日：2013-08-27
申请号：US13251444
申请日：2011-10-03
申请人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
发明人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L21/823456 , H01L21/76229 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/11546 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

8. 发明申请

US20130082318A1 INTEGRATION OF eNVM, RMG, AND HKMG MODULES 有权
标题翻译：整合eNVM，RMG和HKMG模块
公开(公告)号：US20130082318A1
公开(公告)日：2013-04-04
申请号：US13251444
申请日：2011-10-03
申请人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
发明人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
IPC分类号： H01L29/792 , H01L21/762
CPC分类号： H01L21/823456 , H01L21/76229 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/11546 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

9. 发明授权

US07745320B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07745320B2
公开(公告)日：2010-06-29
申请号：US12124177
申请日：2008-05-21
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

10. 发明申请

US20090250762A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS 有权
标题翻译：集成电路系统采用真空间隔
公开(公告)号：US20090250762A1
公开(公告)日：2009-10-08
申请号：US12098751
申请日：2008-04-07
申请人： Huang Liu , Wei Lu , Hai Cong , Alex K.H. See , Hui Peng Koh , Meisheng Zhou
发明人： Huang Liu , Wei Lu , Hai Cong , Alex K.H. See , Hui Peng Koh , Meisheng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
摘要翻译：一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

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