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1. 发明授权

US09034720B2 Litho scanner alignment signal improvement 有权
标题翻译： Litho扫描仪对准信号改善
公开(公告)号：US09034720B2
公开(公告)日：2015-05-19
申请号：US13588018
申请日：2012-08-17
申请人： Hui Liu , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
发明人： Hui Liu , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
IPC分类号： H01L21/76 , G02B6/136 , G03F7/20 , G02B6/124
CPC分类号： G02B6/136 , G02B6/124 , G03F7/70633
摘要： A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.
摘要翻译：提供了一种用于在IC工艺流程中衍射来自光刻扫描仪的入射光的方法和装置。实施例包括在半导体衬底上的第一层中形成衍射光栅; 以及在覆盖所述第一层的第二层中形成多个平版印刷对准标记，其中所述衍射光栅的宽度和长度分别大于或等于所述多个平版印刷对准标记的宽度和长度。

2. 发明授权

US07553678B2 Method for detecting semiconductor manufacturing conditions 有权
标题翻译：检测半导体制造条件的方法
公开(公告)号：US07553678B2
公开(公告)日：2009-06-30
申请号：US11308343
申请日：2006-03-17
申请人： Wen-Zhan Zhou , Jin Yu , Kai-Hung Alex See
发明人： Wen-Zhan Zhou , Jin Yu , Kai-Hung Alex See
IPC分类号： G01R31/26
CPC分类号： G03F7/70625 , G03F7/70508 , H01L22/26 , H01L22/34
摘要： A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a library of relationships between the pitches and the critical dimension of the pattern areas, exposing a test wafer in an unknown manufacturing condition, finding out a relationships between the pitches and the critical dimension of the pattern areas of the test wafer, searching for a most similar relationship in the library, and detecting a set of manufacturing parameters used to expose the test wafer.
摘要翻译：一种用于检测半导体制造条件的方法包括提供具有多个图案区域的光掩模，每个图案区域具有多个具有不同间距的测试线，在不同制造条件下用光掩模曝光多个晶片，测量多个产生间距和图案区域的关键尺寸之间的关系库，使未知制造条件下的测试晶片暴露出来，找出测试晶片的图案区域的间距与临界尺寸之间的关系，在库中搜索最相似的关系，并且检测用于暴露测试晶片的一组制造参数。

3. 发明授权

US08828858B2 Spacer profile engineering using films with continuously increased etch rate from inner to outer surface 有权
标题翻译：使用具有从内到外表面的不断增加的蚀刻速率的膜的间隔轮廓工程
公开(公告)号：US08828858B2
公开(公告)日：2014-09-09
申请号：US13353684
申请日：2012-01-19
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6653 , H01L29/6656
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
摘要翻译：通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

4. 发明授权

US08492236B1 Step-like spacer profile 有权
标题翻译：阶梯状间隔剖面
公开(公告)号：US08492236B1
公开(公告)日：2013-07-23
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

5. 发明授权

US07966142B2 Multi-variable regression for metrology 有权
标题翻译：计量学的多元回归
公开(公告)号：US07966142B2
公开(公告)日：2011-06-21
申请号：US12103690
申请日：2008-04-15
申请人： Wen Zhan Zhou , Zheng Zou , Jasper Goh , Mei Sheng Zhou
发明人： Wen Zhan Zhou , Zheng Zou , Jasper Goh , Mei Sheng Zhou
IPC分类号： G01D21/00 , G06F19/00
CPC分类号： H01L22/12 , G01B21/045 , G01B2210/56 , H01L22/20
摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.
摘要翻译：描述了一种评估测量工具精度的方法。多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。然后执行多变量回归以为数据集生成最佳拟合平面。测定系数（R2值）表示MTUT的精度指标。

6. 发明申请

US20090258445A1 MULTI-VARIABLE REGRESSION FOR METROLOGY 有权
标题翻译：多变量回归计量学
公开(公告)号：US20090258445A1
公开(公告)日：2009-10-15
申请号：US12103690
申请日：2008-04-15
申请人： Wen Zhan ZHOU , Zheng ZOU , Jasper GOH , Mei Sheng ZHOU
发明人： Wen Zhan ZHOU , Zheng ZOU , Jasper GOH , Mei Sheng ZHOU
IPC分类号： G01R35/00 , H01L21/66
CPC分类号： H01L22/12 , G01B21/045 , G01B2210/56 , H01L22/20
摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.
摘要翻译：描述了一种评估测量工具精度的方法。多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。然后执行多变量回归以为数据集生成最佳拟合平面。测定系数（R2值）表示MTUT的精度指标。

7. 发明申请

US20070010092A1 METHOD FOR ELIMINATING BRIDGING DEFECT IN VIA FIRST DUAL DAMASCENE PROCESS 有权
标题翻译：通过第一个双重DAMASCENE过程消除桥梁缺陷的方法
公开(公告)号：US20070010092A1
公开(公告)日：2007-01-11
申请号：US11160688
申请日：2005-07-06
申请人： Wen-Zhan Zhou , Hong Ma , Kuang-Yeh Chang
发明人： Wen-Zhan Zhou , Hong Ma , Kuang-Yeh Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76816
摘要： A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two dense via openings. By doing this, via-to-via bridging defects can be avoided.
摘要翻译：公开了一种通孔第一双镶嵌工艺。当直接在直径大约等于沟槽线的线宽度的两个小直径的密集通孔开口形成沟槽线时，沟槽光致抗蚀剂被偏置在通孔开口上以部分地掩蔽两个致密通孔的侧壁。通过这样做，可以避免通孔到通孔桥接缺陷。

8. 发明申请

US20140050439A1 LITHO SCANNER ALIGNMENT SIGNAL IMPROVEMENT 有权
标题翻译： LITHO扫描仪对准信号改进
公开(公告)号：US20140050439A1
公开(公告)日：2014-02-20
申请号：US13588018
申请日：2012-08-17
申请人： Hui LIU , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
发明人： Hui LIU , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
IPC分类号： G02B6/12 , H01L33/10
CPC分类号： G02B6/136 , G02B6/124 , G03F7/70633
摘要： A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.
摘要翻译：提供了一种用于在IC工艺流程中衍射来自光刻扫描仪的入射光的方法和装置。实施例包括在半导体衬底上的第一层中形成衍射光栅; 以及在覆盖所述第一层的第二层中形成多个平版印刷对准标记，其中所述衍射光栅的宽度和长度分别大于或等于所述多个平版印刷对准标记的宽度和长度。

9. 发明申请

US20130187202A1 SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE 有权
标题翻译：使用膜的间隙轮廓工程，从内部到外表面连续增加的刻蚀速率
公开(公告)号：US20130187202A1
公开(公告)日：2013-07-25
申请号：US13353684
申请日：2012-01-19
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/6653 , H01L29/6656
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
摘要翻译：通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

10. 发明申请

US20130181259A1 STEP-LIKE SPACER PROFILE 有权
公开(公告)号：US20130181259A1
公开(公告)日：2013-07-18
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

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