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1. 发明授权

US07310155B1 Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures 失效
标题翻译：使用在线编程的LER和可靠性结构提取工具独立的线边粗糙度（LER）测量
公开(公告)号：US07310155B1
公开(公告)日：2007-12-18
申请号：US10958149
申请日：2004-10-04
申请人： Luigi Capodieci , Amit P. Marathe , Bhanwar Singh , Ramkumar Subramanian
发明人： Luigi Capodieci , Amit P. Marathe , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B11/04 , G01B11/14
CPC分类号： G01B11/303 , G01N21/47 , G01N21/9501
摘要： A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.
摘要翻译：有助于提取独立于计量装置所有权的线边缘粗糙度测量的系统包括利用与其相关联的已知线边缘粗糙度值图案化到硅上的结构。测量装置从该结构获得线边缘粗糙度测量，并且校正部件基于已知的线边缘粗糙度值与所测量的线边缘粗糙度值之间的比较产生反向函数。测量装置此后可以在硅上图案化的第二结构上测量线边缘粗糙度，并且可以将反函数应用于这种测量的线边缘粗糙度值，以使得能够获得独立于计量装置所有权的线边缘粗糙度测量。

2. 发明授权

US07305645B1 Method for manufacturing place & route based on 2-D forbidden patterns 有权
标题翻译：基于2-D禁止模式制造场所和路线的方法
公开(公告)号：US07305645B1
公开(公告)日：2007-12-04
申请号：US10935488
申请日：2004-09-07
申请人： Luigi Capodieci , Bhanwar Singh , Ramkumar Subramanian
发明人： Luigi Capodieci , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a partially created routing pattern, and a comparing component makes a comparison between the at least partially created routing pattern with one or more patterns in a library of patterns. Routing is controlled based at least in part upon the comparison.
摘要翻译：本发明涉及一种便于控制集成电路中的平面图上的块的路由的系统和/或方法。模式收集器接收部分创建的路由模式，并且比较组件在至少部分创建的路由模式与模式库中的一个或多个模式之间进行比较。至少部分地基于比较来控制路由。

3. 发明授权

US08007631B2 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权
标题翻译：用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合
公开(公告)号：US08007631B2
公开(公告)日：2011-08-30
申请号：US11741991
申请日：2007-04-30
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： C23C10/00 , C29C59/02 , C03C17/22
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

4. 发明授权

US07384569B1 Imprint lithography mask trimming for imprint mask using etch 有权
标题翻译：使用蚀刻的压印掩模的压印光刻掩模修剪
公开(公告)号：US07384569B1
公开(公告)日：2008-06-10
申请号：US10909464
申请日：2004-08-02
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01L21/30 , H01L21/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Disclosed are photolithographic systems and methods, and more particularly systems and methodologies that enhance imprint mask feature resolution. An aspect generates feedback information that facilitates control of imprint mask feature size and resolution via employing a scatterometry system to detect resolution enhancement need, and decreasing imprint mask feature size and increasing resolution of the imprint mask via a trim etch procedure.
摘要翻译：公开了光刻系统和方法，更具体地说，增强了印迹掩模特征分辨率的系统和方法。方面产生反馈信息，其通过采用散射测量系统来检测分辨率增强需求，以及通过修剪蚀刻程序减小压印掩模特征尺寸并增加印迹掩模的分辨率，从而有助于控制印迹掩模特征尺寸和分辨率。

5. 发明申请

US20070283883A1 SYSTEM AND METHOD FOR IMPRINT LITHOGRAPHY TO FACILITATE DUAL DAMASCENE INTEGRATION WITH TWO IMPRINT ACTS 有权
标题翻译：系统和方法，用于绘制两幅印刷动画的双重增强整合
公开(公告)号：US20070283883A1
公开(公告)日：2007-12-13
申请号：US11741991
申请日：2007-04-30
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： C23C10/00
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

6. 发明授权

US07295288B1 Systems and methods of imprint lithography with adjustable mask 有权
标题翻译：带可调面罩的压印光刻系统和方法
公开(公告)号：US07295288B1
公开(公告)日：2007-11-13
申请号：US11000869
申请日：2004-12-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03B27/62 , G03B27/02 , G03B27/20
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.
摘要翻译：提供了通过调节压印光刻掩模的光栅特征来考虑晶片的表面变化的系统和方法。这种调节使用压电元件作为掩模的一部分，其可以在经受电压时改变尺寸（例如，高度变化）和/或移动。因此，通过调节施加到压电元件的电压量，可以获得这些元件的受控膨胀，以适应晶片表面的形貌变化。

7. 发明授权

US07235474B1 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权
标题翻译：用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合
公开(公告)号：US07235474B1
公开(公告)日：2007-06-26
申请号：US10838612
申请日：2004-05-04
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L21/44
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

8. 发明授权

US07158896B1 Real time immersion medium control using scatterometry 失效
标题翻译：实时浸入介质控制采用散射法
公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译：公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。已知的光栅结构被构建在衬底上。实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。

9. 发明授权

US07079975B1 Scatterometry and acoustic based active control of thin film deposition process 失效
标题翻译：薄膜沉积工艺的散射和声学主动控制
公开(公告)号：US07079975B1
公开(公告)日：2006-07-18
申请号：US09845231
申请日：2001-04-30
申请人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
发明人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B11/02 , G01B15/02
CPC分类号： G01B11/0683 , G01B11/0625 , G01B17/025 , G01N21/47 , G01N21/8422 , G01N21/88 , G01N21/94
摘要： A system for monitoring and controlling the deposition of thin films employed in semiconductor fabrication is provided. The system includes one or more acoustic and/or ultrasonic wave sources, each source directing waves onto one or more thin films deposited on a wafer. Waves reflected from the thin film is collected by a monitoring system, which processes the collected waves. Waves passing through the thin film may similarly be collected by the monitoring system, which processes the collected waves. The collected waves are indicative of the presence of impurities and/or defects in the deposited thin film. The monitoring system analyzes and provides the collected wave data to a processor, which determines whether adjustments to thin film deposition parameters are needed. The system also includes a plurality of thin film deposition devices associated with depositing thin films on the wafer. The processor selectively controls thin film deposition parameters and devices to facilitate regulating deposition.
摘要翻译：提供了用于监测和控制用于半导体制造中的薄膜沉积的系统。该系统包括一个或多个声波和/或超声波波束，每个源将波束引导到沉积在晶片上的一个或多个薄膜上。从薄膜反射的波浪由监测系统收集，监测系统处理收集的波。通过薄膜的波浪可以类似地由监测系统收集，监测系统处理所收集的波。收集的波表示沉积的薄膜中存在杂质和/或缺陷。监测系统分析并将收集的波数据提供给处理器，其确定是否需要对薄膜沉积参数进行调整。该系统还包括与在晶片上沉积薄膜相关联的多个薄膜沉积装置。处理器选择性地控制薄膜沉积参数和装置以便于调节沉积。

10. 发明授权

US07078348B1 Dual layer patterning scheme to make dual damascene 失效
标题翻译：双层图案方案制作双镶嵌
公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
申请人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
发明人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译：本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

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