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1. 发明授权

US06677679B1 Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用SiO2 / Sin来防止低k电介质层的铜污染
公开(公告)号：US06677679B1
公开(公告)日：2004-01-13
申请号：US09776749
申请日：2001-02-06
申请人： Lu You , Fei Wang , Dawn M. Hopper
发明人： Lu You , Fei Wang , Dawn M. Hopper
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76831 , H01L21/76834
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，第二蚀刻顶层，介电层和延伸穿过介电层的开口，第一和第二蚀刻停止层以及第一蚀刻停止层扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层上，并且第一蚀刻停止层设置在第二蚀刻停止层上，其间具有第一界面。介电层设置在第一蚀刻停止层上。开口也可以有圆角。侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层和阻挡扩散层可以由氮化硅形成，并且第二蚀刻停止层可以由氧化硅形成。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。还公开了制造半导体器件的方法。

2. 发明授权

US06599839B1 Plasma etch process for nonhomogenous film 有权
标题翻译：非均匀膜的等离子体蚀刻工艺
公开(公告)号：US06599839B1
公开(公告)日：2003-07-29
申请号：US09773906
申请日：2001-02-02
申请人： Calvin T. Gabriel , Lynne A. Okada , Dawn M. Hopper , Suzette K. Pangrle , Fei Wang
发明人： Calvin T. Gabriel , Lynne A. Okada , Dawn M. Hopper , Suzette K. Pangrle , Fei Wang
IPC分类号： H01L21302
CPC分类号： H01L21/31138 , C23F1/12 , H01L21/31116 , H01L21/31144 , H01L21/76802
摘要： A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.
摘要翻译：通过连续改变工艺参数（例如蚀刻剂混合物中的反应剂的量）蚀刻包含非均匀层的复合层。实施例包括用含有氟化有机物，氧气和惰性气体的蚀刻剂混合物蚀刻具有不同浓度碳的氧化硅膜，并且在通过硅蚀刻过程中连续增加和/或减少蚀刻剂混合物中的氧气量氧化膜。

3. 发明授权

US06399446B1 Process for fabricating high density memory cells using a metallic hard mask 有权
标题翻译：使用金属硬掩模制造高密度记忆单元的方法
公开(公告)号：US06399446B1
公开(公告)日：2002-06-04
申请号：US09429722
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/945
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模由钨，钛或氮化钛制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后将硬掩模剥离，优选使用H 2 O 2溶液。

4. 发明授权

US06486029B1 Integration of an ion implant hard mask structure into a process for fabricating high density memory cells 有权
标题翻译：将离子注入硬掩模结构集成到用于制造高密度存储器单元的工艺中
公开(公告)号：US06486029B1
公开(公告)日：2002-11-26
申请号：US09627563
申请日：2000-07-28
申请人： David K. Foote , Bharath Rangarajan , Stephan K. Park , Fei Wang , Dawn M. Hopper , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： David K. Foote , Bharath Rangarajan , Stephan K. Park , Fei Wang , Dawn M. Hopper , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.
摘要翻译：一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

5. 发明授权

US06656830B1 Dual damascene with silicon carbide middle etch stop layer/ARC 有权
标题翻译：双面镶嵌碳化硅中间蚀刻停止层/ ARC
公开(公告)号：US06656830B1
公开(公告)日：2003-12-02
申请号：US09777695
申请日：2001-02-07
申请人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
发明人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.
摘要翻译：通过采用碳化硅中间蚀刻停止层/ ARC，提高了镶嵌加工中沟槽形成的尺寸精度以及因此的金属线宽度。实施例包括使用具有约-0.10至约-0.60的消光系数（k）的碳化硅中蚀刻停止层/ ARC的第一沟槽最后双镶嵌技术。

6. 发明授权

US06436766B1 Process for fabricating high density memory cells using a polysilicon hard mask 有权
标题翻译：使用多晶硅硬掩模制造高密度存储单元的方法
公开(公告)号：US06436766B1
公开(公告)日：2002-08-20
申请号：US09430493
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模优选由多晶硅或硅制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后去除硬掩模，优选使用等离子体蚀刻工艺。

7. 发明授权

US07256499B1 Ultra low dielectric constant integrated circuit system 有权
标题翻译：超低介电常数集成电路系统
公开(公告)号：US07256499B1
公开(公告)日：2007-08-14
申请号：US11230985
申请日：2005-09-19
申请人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
发明人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.
摘要翻译：提供了一种集成电路，包括在半导体衬底上形成多孔超低介电常数介电层，并在超低介电常数介电层中形成开口。形成电介质衬垫以使开口线对，以覆盖超低介电常数电介质层中的孔，并且沉积阻挡层以对电介质衬垫进行排列，并且沉积导体芯以填充阻挡层上的开口。

8. 发明授权

US07208418B1 Sealing sidewall pores in low-k dielectrics 有权
标题翻译：密封低k电介质中的侧壁孔
公开(公告)号：US07208418B1
公开(公告)日：2007-04-24
申请号：US10728774
申请日：2003-12-08
申请人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
发明人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
IPC分类号： H01L21/311
CPC分类号： H01L21/76831
摘要： Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.
摘要翻译：通过在阻挡金属层沉积之前密封侧壁孔隙率来减少由于低k介电孔隙导致的阻挡金属层不连续性或间隙。实施例包括通过沉积溶胀剂，粘合促进剂或低k材料的附加层来密封侧壁孔隙。

9. 发明授权

US07038320B1 Single damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的单镶嵌一体化方案
公开(公告)号：US07038320B1
公开(公告)日：2006-05-02
申请号：US09785445
申请日：2001-02-20
申请人： Lu You , Fei Wang , Minh Van Ngo
发明人： Lu You , Fei Wang , Minh Van Ngo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76814 , H01L21/76834
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上并与第一扩散阻挡层隔开，并且介电层设置在第一蚀刻停止层上。通孔也可以有圆角。第二蚀刻停止层也可以设置在第一扩散阻挡层和第一蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

10. 发明授权

US06586842B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06586842B1
公开(公告)日：2003-07-01
申请号：US09793993
申请日：2001-02-28
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L2352
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

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