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1. 发明授权

US06939793B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06939793B1
公开(公告)日：2005-09-06
申请号：US10422784
申请日：2003-04-25
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

2. 发明授权

US06586842B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06586842B1
公开(公告)日：2003-07-01
申请号：US09793993
申请日：2001-02-28
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L2352
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

3. 发明授权

US06518185B1 Integration scheme for non-feature-size dependent cu-alloy introduction 有权
标题翻译：非特征尺寸依赖的Cu合金介绍的集成方案
公开(公告)号：US06518185B1
公开(公告)日：2003-02-11
申请号：US10127521
申请日：2002-04-22
申请人： Pin-Chin Connie Wang , Fei Wang , Kashmir Sahota , Steven Avanzino , Amit Marathe , Matthew Buynoski , Ercan Adem , Christy Woo
发明人： Pin-Chin Connie Wang , Fei Wang , Kashmir Sahota , Steven Avanzino , Amit Marathe , Matthew Buynoski , Ercan Adem , Christy Woo
IPC分类号： H01L2144
CPC分类号： H01L21/76877
摘要： In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.
摘要翻译：在本发明的半导体装置的制造方法中，在介质层中设置不同结构（例如不同的纵横比）的开口。基本上未掺杂的铜沉积在电介质层上，填充开口并在电介质层上方延伸，开口的不同构型提供通常为非平面的基本未掺杂的铜的上表面。去除基本上未掺杂的铜的一部分以提供其基本平坦的上表面，并且在基本未掺杂的铜的上表面上沉积掺杂的铜层。进行退火步骤以将掺杂元素扩散到开口中的铜中。

4. 发明授权

US06663787B1 Use of ta/tan for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用ta / tan来防止低k电介质层的铜污染
公开(公告)号：US06663787B1
公开(公告)日：2003-12-16
申请号：US09776747
申请日：2001-02-06
申请人： Lu You , Christy Woo , Pin Chin Connie Wang
发明人： Lu You , Christy Woo , Pin Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L21/76831 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride. Metal within the opening form a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，电介质层和延伸穿过介电层的开口，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。开口也可以有圆角。侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由不同于第一阻挡层的材料形成，并且第一阻挡层的材料可以选自钽，钛，氮化钽，氮化钛和氮化钨。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。还公开了制造半导体器件的方法。

5. 发明申请

US20080182407A1 METHOD OF FORMING VIAS IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成VIAS的方法
公开(公告)号：US20080182407A1
公开(公告)日：2008-07-31
申请号：US11669700
申请日：2007-01-31
申请人： Jun Zhai , Christy Woo , Kok-Yong Yiang , Paul R. Besser , Richard C. Blish , Christine Hau-Reige
发明人： Jun Zhai , Christy Woo , Kok-Yong Yiang , Paul R. Besser , Richard C. Blish , Christine Hau-Reige
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76852 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.
摘要翻译：通孔形成为与导电线接触，由此通孔偏离导线，使得通孔延伸超过导线。根据具体实施例，通孔的一部分接触导线的侧壁。

6. 发明授权

US08723321B2 Copper interconnects with improved electromigration lifetime 有权
标题翻译：铜互连具有改善的电迁移寿命
公开(公告)号：US08723321B2
公开(公告)日：2014-05-13
申请号：US11448788
申请日：2006-06-08
申请人： Christy Woo , Jun “Charlie” Zhai , Paul Besser , Kok-Yong Yiang , Richard C. Blish , Christine Hau-Riege
发明人： Christy Woo , Jun “Charlie” Zhai , Paul Besser , Kok-Yong Yiang , Richard C. Blish , Christine Hau-Riege
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.
摘要翻译：通过图案化之后Cu线和其上的覆盖层之间的剥离应力通过改变通孔的形状并定位通孔来减小，以增加通孔和线边缘之间的空间，从而增加电迁移寿命。实施例包括改变通孔的形状，如通过形成椭圆形或矩形形状的通孔，使得椭圆形的短轴与线之间的比例或矩形的宽度与线宽的比率小于约0.7。

7. 发明授权

US07005387B2 Method for preventing an increase in contact hole width during contact formation 失效
标题翻译：防止接触形成时接触孔宽度增大的方法
公开(公告)号：US07005387B2
公开(公告)日：2006-02-28
申请号：US10705631
申请日：2003-11-08
申请人： Dawn Hopper , Hiroyuki Kinoshita , Christy Woo
发明人： Dawn Hopper , Hiroyuki Kinoshita , Christy Woo
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76814 , H01L21/76865
摘要： According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.
摘要翻译：根据一个示例性实施例，用于在位于半导体管芯中的硅化物层上形成接触的方法包括在接触孔的侧壁和位于接触孔的底部的自然氧化物层上沉积阻挡层的步骤，其中侧壁由电介质层中的接触孔限定。可以优化将阻挡层沉积在接触孔的侧壁和自然氧化物层上的步骤，使得阻挡层在接触孔的顶部具有比接触孔底部的厚度更大的厚度。根据该示例性实施例，该方法还包括去除位于接触孔底部的阻挡层和自然氧化物层的一部分以露出硅化物层的步骤。

8. 发明授权

US07033888B2 Engineered metal gate electrode 有权
标题翻译：工程金属栅电极
公开(公告)号：US07033888B2
公开(公告)日：2006-04-25
申请号：US10806117
申请日：2004-03-23
申请人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
发明人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/4966
摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.
摘要翻译：形成具有固有电场的金属栅电极，以改变晶体管的功函数和阈值电压。实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积一层或多层氮化钽，使氮含量从邻近栅介质层的层的底部向上增加。其他实施例包括通过掺杂一个或多个金属层并形成金属合金来形成本征电场以控制功函数。实施例还包括在形成金属栅电极时使用阻挡层。

9. 发明申请

US20050224979A1 CU INTERCONNECTS WITH COMPOSITE BARRIER LAYERS FOR WAFER-TO-WAFER UNIFORMITY 有权
标题翻译：具有复合阻挡层的CU互连用于波形到波长均匀性
公开(公告)号：US20050224979A1
公开(公告)日：2005-10-13
申请号：US10811860
申请日：2004-03-30
申请人： Amit Marathe , Connie Wang , Christy Woo
发明人： Amit Marathe , Connie Wang , Christy Woo
IPC分类号： H01L21/768 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846
摘要： A composite α-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous α-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of α-Ta, e.g., as at a thickness of bout 50 Å to about 100 Å. Embodiments include composite barrier layers having a thickness ratio of α-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.
摘要翻译：在Cu互连中形成复合α-Ta /分级氮化钽/ TaN阻挡层，其具有为提高晶片到晶片的均匀性，电迁移电阻和可靠性，降低的接触电阻和增加的工艺裕度而设计的结构。实施例包括在包含Cu的低k层间电介质中的双镶嵌结构和在低k材料上包含TaN的初始层的复合势垒层，初始TaN层上的氮化钽梯度层和连续的α-Ta 层叠在梯度氮化钽层上。实施方案包括以足以确保α-Ta沉积的厚度形成初始TaN层，例如在50至大约的厚度。实施例包括厚度比为α-Ta和梯度氮化钽的复合阻挡层：初始TaN为约2.5:1至约3.5:1，以提高电迁移阻力和晶片与晶片的均匀性。

10. 发明申请

US20070284748A1 Copper interconnects with improved electromigration lifetime 有权
标题翻译：铜互连具有改善的电迁移寿命
公开(公告)号：US20070284748A1
公开(公告)日：2007-12-13
申请号：US11448788
申请日：2006-06-08
申请人： Christy Woo , Jun "Charlie" Zhai , Paul Besser , Kok-Yong Yiang , Richard C. Blish , Christine Hau-Riege
发明人： Christy Woo , Jun "Charlie" Zhai , Paul Besser , Kok-Yong Yiang , Richard C. Blish , Christine Hau-Riege
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.
摘要翻译：通过图案化之后Cu线和其上的覆盖层之间的剥离应力通过改变通孔的形状并定位通孔来减小，以增加通孔和线边缘之间的空间，从而增加电迁移寿命。实施例包括改变通孔的形状，如通过形成椭圆形或矩形形状的通孔，使得椭圆形的短轴与线之间的比例或矩形的宽度与线宽的比率小于约0.7。

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