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1. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

2. 发明授权

US06541815B1 High-density dual-cell flash memory structure 失效
标题翻译：高密度双单元闪存结构
公开(公告)号：US06541815B1
公开(公告)日：2003-04-01
申请号：US09974968
申请日：2001-10-11
申请人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
发明人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/7885
摘要： A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches. The wordlines are in contact with a top surface of each control gate region.
摘要翻译：提供了一种2F2闪存单元结构及其制造方法。 2F2闪存单元结构包括其中形成有多个沟槽的含Si衬底。每个沟槽具有延伸到底壁，长度和包括每个段的两个存储单元元件的单独段的侧壁。每个存储单元元件包括（i）具有形成在每个沟槽侧壁的一部分上的L形栅极的浮栅区域; （ii）重叠在每个沟槽的底壁处的L形门的一侧并沿多个沟槽的整个长度延伸的程序线; 和（iii）覆盖浮栅区域的控制栅极区域。控制栅极区域包括形成在沟槽的侧壁的与浮动栅极区域耦合的部分上的栅极。所述存储单元结构还包括形成在所述含Si半导体衬底中的位线邻接每个沟槽段的位线扩散区; 和与沟槽正交的字线。字线与每个控制栅极区域的顶表面接触。

3. 发明授权

US06544874B2 Method for forming junction on insulator (JOI) structure 失效
标题翻译：用于形成绝缘体结（JOI）结构的方法
公开(公告)号：US06544874B2
公开(公告)日：2003-04-08
申请号：US09928759
申请日：2001-08-13
申请人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L213205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译：提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。

4. 发明授权

US06534807B2 Local interconnect junction on insulator (JOI) structure 失效
标题翻译：局部互连绝缘体结（JOI）结构
公开(公告)号：US06534807B2
公开(公告)日：2003-03-18
申请号：US09928738
申请日：2001-08-13
申请人： Jack A. Mandelman , Dong Gan , Chung H. Lam
发明人： Jack A. Mandelman , Dong Gan , Chung H. Lam
IPC分类号： H01L2980
CPC分类号： H01L27/11 , H01L21/76895 , H01L21/823475 , H01L27/1104
摘要： A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. An alternative JOI structure and cell layout of the present invention includes at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region.
摘要翻译： JOI结构和电池布局包括存在于半导体衬底顶部的至少一个图案化栅极叠层区域，所述半导体衬底具有彼此相邻的相反掺杂极性的源/漏扩散区域，所述源极/漏极扩散区域位于绝缘体顶部所述绝缘层不存在于所述至少一个图案化的栅堆叠区域之下。本发明的替代的JOI结构和电池布局包括存在于半导体衬底顶部的至少一个图案化栅堆叠区域，所述半导体衬底至少包含存在于嵌入其中的绝缘层顶部的源极/漏极扩散区域以外的导电区域，绝缘层不存在于所述至少一个图案化的栅堆叠区域之下，其中所述导电区域与存在于所述半导体衬底中的源极/漏极延伸区域的垂直侧壁接触，位于所述至少一个图案化栅极堆叠区域之下。

5. 发明授权

US08902690B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
标题翻译：需要单极编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

6. 发明授权

US08687398B2 Sense scheme for phase change material content addressable memory 有权
标题翻译：相变材料内容可寻址存储器的感应方案
公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译：一种用于感测内容可寻址存储器中匹配线的感测电路和方法。感测电路包括电反馈回路中电耦合到匹配线的反相器。逆变器包括匹配线的反相阈值。在预充电阶段期间，将匹配线充电至基本上第一电压阈值。当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

7. 发明申请

US20140052900A1 MEMORY CONTROLLER FOR MEMORY WITH MIXED CELL ARRAY AND METHOD OF CONTROLLING THE MEMORY 有权
公开(公告)号：US20140052900A1
公开(公告)日：2014-02-20
申请号：US13610830
申请日：2012-09-11
申请人： Bing Dai , Chung H. Lam , Jing Li
发明人： Bing Dai , Chung H. Lam , Jing Li
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F1/32 , G06F12/0246
摘要： A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

8. 发明申请

US20130314983A1 DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY 有权
公开(公告)号：US20130314983A1
公开(公告)日：2013-11-28
申请号：US13478932
申请日：2012-05-23
申请人： Chung H. Lam , Jing Li , Binquan Luan , Glenn J. Martyna , Dennis M. Newns
发明人： Chung H. Lam , Jing Li , Binquan Luan , Glenn J. Martyna , Dennis M. Newns
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C11/16 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/009 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.

9. 发明授权

US08536675B2 Thermally insulated phase change material memory cells 有权
标题翻译：热绝缘相变材料存储单元
公开(公告)号：US08536675B2
公开(公告)日：2013-09-17
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L23/52 , H01L29/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译：一种存储单元结构及其形成方法。该方法包括在电介质层内形成孔。孔形成在导电底部电极的中心上方。该方法包括沿孔的至少一个侧壁沉积绝热层。绝热层将热量从相变电流隔离成孔的体积。在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。该方法还包括在相变材料上形成导电顶电极。

10. 发明授权

US08421194B2 Sub-lithographic printing method 失效
标题翻译：亚平版印刷法
公开(公告)号：US08421194B2
公开(公告)日：2013-04-16
申请号：US13006403
申请日：2011-01-13
申请人： Chung H. Lam , Hemantha K. Wickramasinghe
发明人： Chung H. Lam , Hemantha K. Wickramasinghe
IPC分类号： H01L29/06
CPC分类号： H01L21/0337
摘要： A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.
摘要翻译：沟槽结构和集成电路，其包括衬底中的次光刻沟槽结构。在一个实施例中，沟槽结构是通过用光刻掩膜形成一组沟槽而形成的，并且用一组间隔块块填充该组沟槽，该组间隔块包括彼此分离地可拆卸的两个交替间隔物材料。在一个实施例中，形成的沟槽结构是光刻掩模的特征尺寸的厚度的十分之一。沟槽结构的尺寸取决于用于形成一组步进间隔块的间隔材料层的厚度和数量。间隔材料层的数量为n / 2，每个间隔材料层的厚度为光刻掩模的特征尺寸的十分之一。

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