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1. 发明申请

US20200004679A1 SECURE LOGICAL-TO-PHYSICAL CACHING 审中-公开
公开(公告)号：US20200004679A1
公开(公告)日：2020-01-02
申请号：US16023485
申请日：2018-06-29
申请人： Zoltan Szubbocsev , Alberto Troia , Federico Tiziani , Antonino Mondello
发明人： Zoltan Szubbocsev , Alberto Troia , Federico Tiziani , Antonino Mondello
IPC分类号： G06F12/0802 , G06F12/1009 , G06F12/02 , H04L9/08 , H04L9/32
摘要： Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

2. 发明申请

US20120311415A1 METHOD AND DEVICE FOR DETECTING POSSIBLE CORRUPTION OF SECTOR PROTECTION INFORMATION OF A NON-VOLATILE MEMORY STORED IN AN ON BOARD VOLATILE MEMORY ARRAY AT POWER-ON 审中-公开
标题翻译：用于检测在上电时的易失性存储器阵列中存储的非易失性存储器的部门保护信息可能的损坏的方法和装置
公开(公告)号：US20120311415A1
公开(公告)日：2012-12-06
申请号：US13589509
申请日：2012-08-20
申请人： Antonino MONDELLO
发明人： Antonino MONDELLO
IPC分类号： H03M13/09
CPC分类号： G11C16/22 , G11C8/20 , G11C16/04 , G11C29/52 , G11C2029/0407
摘要： A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is downloaded in the memory array at every power-on of the memory device. The memory array includes at least two additional columns containing preset logic information physically adjacent to the columns containing the downloaded information. A logic circuit is input with the logic information read from the additional check columns for checking the integrity of the preset logic information content of the check columns. An integrity check signal is output by the logic circuit.
摘要翻译：非易失性存储器件包括可寻址扇区和辅助易失性存储器阵列。辅助易失性存储器阵列将保护信息存储在存储器的用户无法访问的可寻址扇区中。在存储器件的每次上电时，保护信息被下载到存储器阵列中。存储器阵列包括至少两个附加列，其包含物理上与包含下载信息的列物理相邻的预置逻辑信息。输入逻辑电路，其中从附加检查列读取的逻辑信息用于检查检查列的预设逻辑信息内容的完整性。完整性检查信号由逻辑电路输出。

3. 发明授权

US07646655B2 Memory device with fail search and redundancy 有权
标题翻译：具有故障搜索和冗余的内存设备
公开(公告)号：US07646655B2
公开(公告)日：2010-01-12
申请号：US11780581
申请日：2007-07-20
申请人： Antonino Mondello , Alessandro Tumminia , Luigi Buono
发明人： Antonino Mondello , Alessandro Tumminia , Luigi Buono
IPC分类号： G11C7/00
CPC分类号： G11C29/48 , G11C16/04 , G11C29/16 , G11C29/4401 , G11C29/82
摘要： An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.
摘要翻译：自动冗余系统可以利用现有的芯片上的微处理器管理系统来自主地执行，而不与外部测试机通信，操作：根据一个或多个预先建立的测试模式将数据写入存储器阵列，连续验证数据从存储器阵列读取，并用等效的冗余结构代替存储器阵列的故障元件。逻辑结构可以检测并存储在输出数据路径上游的存储器阵列故障。因此，与故障相关的数据收集可以更快地完成，并且除了传达冗余处理的执行结束之外，还不与测试机进行任何交互。

4. 发明申请

US20080013387A1 AUTOMATIC REGULATION METHOD FOR THE REFERENCE SOURCES IN A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING MEMORY DEVICE 有权
标题翻译：用于非易失性存储器件和相应存储器件中的参考源的自动调节方法
公开(公告)号：US20080013387A1
公开(公告)日：2008-01-17
申请号：US11771677
申请日：2007-06-29
申请人： Antonino Mondello , Michelangelo Pisasale
发明人： Antonino Mondello , Michelangelo Pisasale
IPC分类号： G11C5/14
CPC分类号： G11C29/02 , G11C16/04 , G11C29/021 , G11C29/028
摘要： A method and a relative automatic regulation device regulate the reference sources in a non-volatile memory device, for example a flash memory. The method includes the following steps: providing, in the memory device, a regulation device of the reference sources and at least one start command for the entry in regulation mode; providing, on the device, at least one command for the selection of a corresponding reference source to be regulated; applying an external reference signal; starting the automatic regulation step by means of said command; detecting the result of the regulation step by means of a logic output of the memory device; if the result of the regulation of a given source is positive, proceeding, by means of the same process steps, with the regulation of another source.
摘要翻译：一种方法和相对自动调节装置调节非易失性存储器件（例如闪存）中的参考源。该方法包括以下步骤：在存储器装置中提供参考源的调节装置和在调节模式下进入的至少一个启动命令; 在所述设备上提供用于选择要被调节的对应参考源的至少一个命令; 应用外部参考信号; 通过所述命令开始自动调节步骤; 通过存储器件的逻辑输出来检测调节步骤的结果; 如果给定来源的规定的结果是积极的，则通过相同的处理步骤，对另一来源的规定进行处理。

5. 发明授权

US07167394B2 Sense amplifier for reading a cell of a non-volatile memory device 失效
标题翻译：用于读取非易失性存储器件单元的读出放大器
公开(公告)号：US07167394B2
公开(公告)日：2007-01-23
申请号：US11121616
申请日：2005-05-04
申请人： Michele La Placa , Antonino Mondello
发明人： Michele La Placa , Antonino Mondello
IPC分类号： G11C11/34
CPC分类号： G11C16/28
摘要： A sense amplifier for reading a non-volatile memory cell includes a bitline current path connected to a non-volatile memory cell to be read, and a reference current path connected to a reference memory cell. A current mirror includes an input transistor and a corresponding input node, and an output transistor and a corresponding output node. The current mirror converts currents in the reference current path and the bitline current path to respective voltages on the input and output nodes. An equalization circuit equalizes the voltages on the input and output nodes of the current mirror and is activated by a command signal. The equalization circuit includes a switch controlled by the command signal, and a diode-connected load transistor connected in parallel to the output transistor of the current mirror and connected to the output node thereof through the switch. A current steering path draws from the bitline current path a current when enabled by the command signal so that the load transistor establishes a desired voltage on the output node.
摘要翻译：用于读取非易失性存储单元的读出放大器包括连接到要读取的非易失性存储器单元的位线电流路径和连接到参考存储器单元的参考电流路径。电流镜包括输入晶体管和相应的输入节点，以及输出晶体管和相应的输出节点。电流镜将参考电流路径中的电流和位线电流路径转换为输入和输出节点上的相应电压。均衡电路均衡电流镜的输入和输出节点上的电压，并由命令信号激活。均衡电路包括由指令信号控制的开关和与电流镜的输出晶体管并联连接的二极管连接的负载晶体管，并通过开关连接到其输出节点。当命令信号使能时，当前的转向路径从位线电流通路中抽出电流，使得负载晶体管在输出节点上建立所需的电压。

6. 发明申请

US20070016735A1 Flash memory device with improved management of protection information 有权
标题翻译：闪存设备具有改进的保护信息管理功能
公开(公告)号：US20070016735A1
公开(公告)日：2007-01-18
申请号：US11432301
申请日：2006-05-10
申请人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
发明人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00 , G11C16/04 , G11C11/34
CPC分类号： G11C16/22 , G06F12/1433 , G06F21/6209 , G06F21/79 , G06F2212/2022
摘要： A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.
摘要翻译：闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。

7. 发明申请

US20050249007A1 Sense amplifier for reading a cell of a non-volatile memory device 失效
标题翻译：用于读取非易失性存储器件单元的读出放大器
公开(公告)号：US20050249007A1
公开(公告)日：2005-11-10
申请号：US11121616
申请日：2005-05-04
申请人： Michele La Placa , Antonino Mondello
发明人： Michele La Placa , Antonino Mondello
IPC分类号： G11C7/02 , G11C16/28
CPC分类号： G11C16/28
摘要： A sense amplifier for reading a non-volatile memory cell includes a bitline current path connected to a non-volatile memory cell to be read, and a reference current path connected to a reference memory cell. A current mirror includes an input transistor and a corresponding input node, and an output transistor and a corresponding output node. The current mirror converts currents in the reference current path and the bitline current path to respective voltages on the input and output nodes. An equalization circuit equalizes the voltages on the input and output nodes of the current mirror and is activated by a command signal. The equalization circuit includes a switch controlled by the command signal, and a diode-connected load transistor connected in parallel to the output transistor of the current mirror and connected to the output node thereof through the switch. A current steering path draws from the bitline current path a current when enabled by the command signal so that the load transistor establishes a desired voltage on the output node.
摘要翻译：用于读取非易失性存储单元的读出放大器包括连接到要读取的非易失性存储器单元的位线电流路径和连接到参考存储器单元的参考电流路径。电流镜包括输入晶体管和相应的输入节点，以及输出晶体管和相应的输出节点。电流镜将参考电流路径中的电流和位线电流路径转换为输入和输出节点上的相应电压。均衡电路均衡电流镜的输入和输出节点上的电压，并由命令信号激活。均衡电路包括由指令信号控制的开关和与电流镜的输出晶体管并联连接的二极管连接的负载晶体管，并通过开关连接到其输出节点。当命令信号使能时，当前的转向路径从位线电流通路中抽出电流，使得负载晶体管在输出节点上建立所需的电压。

8. 发明授权

US06650569B2 Boost device for nonvolatile memories with an integrated stand-by charge pump 有权
公开(公告)号：US06650569B2
公开(公告)日：2003-11-18
申请号：US10076134
申请日：2002-02-13
申请人： Martino Angelica , Antonino Mondello
发明人： Martino Angelica , Antonino Mondello
IPC分类号： G11C1604
CPC分类号： G11C16/30 , G11C5/145
摘要： The boost device comprises a charge pump circuit having an input and a main output between which an input stage, an intermediate stage and a main output stage are cascade connected. The charge pump circuit also comprises a stand-by output stage having an input node connected to an output node of said intermediate stage and an output node connected to a stand-by output of the charge pump circuit. The boost device further comprises a phase generator stage having a signal input receiving a suitable clock signal generated by a clock generator stage and output terminals generating phase signals supplied to phase inputs of the charge pump circuit.

9. 发明授权

US08250314B2 Method and device for checking sector protection information of a non-volatile memory 有权
标题翻译：用于检查非易失性存储器的扇区保护信息的方法和装置
公开(公告)号：US08250314B2
公开(公告)日：2012-08-21
申请号：US11693360
申请日：2007-03-29
申请人： Antonino Mondello
发明人： Antonino Mondello
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C16/22 , G11C8/20 , G11C16/04 , G11C29/52 , G11C2029/0407
摘要： A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is downloaded in the memory array at every power-on of the memory device. The memory array includes at least two additional columns containing preset logic information physically adjacent to the columns containing the downloaded information. A logic circuit is input with the logic information read from the additional check columns for checking the integrity of the preset logic information content of the check columns. An integrity check signal is output by the logic circuit.
摘要翻译：非易失性存储器件包括可寻址扇区和辅助易失性存储器阵列。辅助易失性存储器阵列将保护信息存储在存储器的用户无法访问的可寻址扇区中。在存储器件的每次上电时，保护信息被下载到存储器阵列中。存储器阵列包括至少两个附加列，其包含物理上与包含下载信息的列物理相邻的预置逻辑信息。输入逻辑电路，其中从附加检查列读取的逻辑信息用于检查检查列的预设逻辑信息内容的完整性。完整性检查信号由逻辑电路输出。

10. 发明授权

US07567470B2 Automatic regulation method for the reference sources in a non-volatile memory device and corresponding memory device 有权
标题翻译：用于非易失性存储器件和相应存储器件中的参考源的自动调节方法
公开(公告)号：US07567470B2
公开(公告)日：2009-07-28
申请号：US11771677
申请日：2007-06-29
申请人： Antonino Mondello , Michelangelo Pisasale
发明人： Antonino Mondello , Michelangelo Pisasale
IPC分类号： G11C5/14
CPC分类号： G11C29/02 , G11C16/04 , G11C29/021 , G11C29/028
摘要： A method and a relative automatic regulation device regulate the reference sources in a non-volatile memory device, for example a flash memory. The method includes the following steps: providing, in the memory device, a regulation device of the reference sources and at least one start command for the entry in regulation mode; providing, on the device, at least one command for the selection of a corresponding reference source to be regulated; applying an external reference signal; starting the automatic regulation step by means of said command; detecting the result of the regulation step by means of a logic output of the memory device; if the result of the regulation of a given source is positive, proceeding, by means of the same process steps, with the regulation of another source.
摘要翻译：一种方法和相对自动调节装置调节非易失性存储器件（例如闪存）中的参考源。该方法包括以下步骤：在存储器装置中提供参考源的调节装置和在调节模式下进入的至少一个启动命令; 在所述设备上提供用于选择要被调节的对应参考源的至少一个命令; 应用外部参考信号; 通过所述命令开始自动调节步骤; 通过存储器件的逻辑输出来检测调节步骤的结果; 如果给定来源的规定的结果是积极的，则通过相同的处理步骤，对另一来源的规定进行处理。

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