专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06339551B1 Semiconductor device with selectable pads 有权
标题翻译：具有可选焊盘的半导体器件
公开(公告)号：US06339551B1
公开(公告)日：2002-01-15
申请号：US09560514
申请日：2000-04-27
申请人： Simone Bartoli , Mauro Sali , Claudio Nava , Antonio Russo
发明人： Simone Bartoli , Mauro Sali , Claudio Nava , Antonio Russo
IPC分类号： G11C700
CPC分类号： G11C7/10 , G11C5/04 , G11C5/063 , G11C2207/105
摘要： A semiconductor device includes at least two pads for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers each connected to each one of said pads, at least one multiplexer connected to said pads by means of said uncoupling buffers and at least one memory element suitable to generate a configuration signal operating on said multiplexer and said uncoupling buffers to selectively enable one or the other of said pads.
摘要翻译：半导体器件包括用于输入外部信号和/或用于输出来自所述半导体器件的信号的至少两个焊盘，至少两个非耦合缓冲器，每个至少两个非耦合缓冲器连接到每个所述焊盘，至少一个多路复用器通过所述解耦缓冲器的装置和适于产生在所述多路复用器和所述非耦合缓冲器上操作的配置信号的至少一个存储元件，以选择性地使能所述焊盘中的一个或另一个。

2. 发明授权

US07965561B2 Row selector occupying a reduced device area for semiconductor memory devices 有权
标题翻译：行选择器占用半导体存储器件的减少的器件面积
公开(公告)号：US07965561B2
公开(公告)日：2011-06-21
申请号：US11672857
申请日：2007-02-08
申请人： Pierguido Garofalo , Efrem Bolandrina , Claudio Nava
发明人： Pierguido Garofalo , Efrem Bolandrina , Claudio Nava
IPC分类号： G11C16/08
CPC分类号： G11C8/10
摘要： A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address codes of the plurality of memory cells and to generate a plurality of decoding and selecting signals in response to the address codes. A plurality of second decoding circuits are coupled to the first decoding circuit and operable to generate driving signals for the memory cell address signal lines based at least in part on the plurality of decoding and selecting signals. A voltage shifting circuit is operable to generate a shift in the voltage of the plurality of decoding and selecting signals for generating a plurality of shifted voltage decoding and selecting signals and to provide the shifted decoding and selecting signals to the plurality of second decoding signals for generating the drive signals.
摘要翻译：公开了一种具有分组在至少两个存储器扇区中的多个存储器单元的存储器件。第一解码电路，用于接收所述多个存储单元的地址码，并响应于地址码产生多个解码和选择信号。多个第二解码电路耦合到第一解码电路，并且可操作以至少部分地基于多个解码和选择信号来产生用于存储单元地址信号线的驱动信号。电压移位电路可操作以产生用于产生多个移位电压解码和选择信号的多个解码和选择信号的电压偏移，并向多个第二解码信号提供移位的解码和选择信号以产生驱动信号。

3. 发明授权

US07911290B2 Transmission line system for a digital signal having a transfer bus shielded from disturbances by at least one conductive line 有权
标题翻译：一种用于数字信号的传输线系统，具有通过至少一条导线屏蔽干扰的传输总线
公开(公告)号：US07911290B2
公开(公告)日：2011-03-22
申请号：US11560704
申请日：2006-11-16
申请人： Daniele Vimercati , Claudio Nava , Christophe Laurent
发明人： Daniele Vimercati , Claudio Nava , Christophe Laurent
IPC分类号： H01P5/02
CPC分类号： H04L25/0266 , H04B3/56 , H04B2203/5487
摘要： A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.
摘要翻译：用于数字信号的传输系统包括发射机和通过传输总线连接到其的接收机。传输系统包括与传输总线电容耦合的至少一个导线。

4. 发明申请

US20070133666A1 TRANSMISSION SYSTEM OF A DIGITAL SIGNAL 有权
标题翻译：数字信号传输系统
公开(公告)号：US20070133666A1
公开(公告)日：2007-06-14
申请号：US11560704
申请日：2006-11-16
申请人： Daniele Vimercati , Claudio Nava , Christophe Laurent
发明人： Daniele Vimercati , Claudio Nava , Christophe Laurent
IPC分类号： H04L5/16
CPC分类号： H04L25/0266 , H04B3/56 , H04B2203/5487
摘要： A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.
摘要翻译：用于数字信号的传输系统包括发射机和通过传输总线连接到其的接收机。传输系统包括与传输总线电容耦合的至少一个导线。

5. 发明授权

US07596023B2 Memory device employing three-level cells and related methods of managing 有权
标题翻译：采用三层单元的存储器件及相关的管理方法
公开(公告)号：US07596023B2
公开(公告)日：2009-09-29
申请号：US11934144
申请日：2007-11-02
申请人： Alessandro Magnavacca , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
发明人： Alessandro Magnavacca , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/3427
摘要： A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.
摘要翻译：存储器件可以包括可寻址的三电平单元的阵列，编码电路以三比特串输入，并且基于代码产生相应的三进制串，并且编程电路用三进制串输入并以相应的对存储的三级细胞。存储装置还可以包括读取电路，读取相应的三电平单元对中的存储的三进制串，以及基于所存储的三进制字符串输入的解码电路，并且基于该代码生成三位的相应串。

6. 发明申请

US20080106937A1 MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS AND RELATED METHODS OF MANAGING 有权
标题翻译：使用三级细胞的记忆装置和相关的管理方法
公开(公告)号：US20080106937A1
公开(公告)日：2008-05-08
申请号：US11934144
申请日：2007-11-02
申请人： Alessandro MAGNAVACCA , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
发明人： Alessandro MAGNAVACCA , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/3427
摘要： A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.
摘要翻译：存储器件可以包括可寻址的三电平单元的阵列，编码电路以三比特串输入，并且基于代码产生相应的三进制串，并且编程电路用三进制串输入并以相应的对存储的三级细胞。存储装置还可以包括读取电路，读取相应的三电平单元对中的存储的三进制串，以及基于所存储的三进制字符串输入的解码电路，并且基于该代码生成三位的相应串。

7. 外观设计

USD523794S1 Caliper for disc brakes 有权
公开(公告)号：USD523794S1
公开(公告)日：2006-06-27
申请号：US29217900
申请日：2004-11-24
申请人： Fortunato Strumbo , Claudio Nava
设计人： Fortunato Strumbo , Claudio Nava

8. 发明申请

US20070195605A1 ROW SELECTOR WITH REDUCED AREA OCCUPATION FOR SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：具有减少区域占用半导体存储器件的选择器
公开(公告)号：US20070195605A1
公开(公告)日：2007-08-23
申请号：US11672857
申请日：2007-02-08
申请人： Pierguido Garofalo , Efrem Bolandrina , Claudio Nava
发明人： Pierguido Garofalo , Efrem Bolandrina , Claudio Nava
IPC分类号： G11C11/34
CPC分类号： G11C8/10
摘要： A memory device including a plurality of memory cells, said memory cells being grouped in at least two memory sectors. In each memory sector the memory cells are arranged according to a plurality of alignments of memory cells. A respective memory cell access signal line is associated with each alignment. A first decoding circuit is adapted to receive an address code of the memory cells and in response thereto asserts a plurality of decoding and selecting signals common to said at least two memory sectors. A respective second decoding circuit, associated with each one of the at least two memory sectors, is operatively coupled to the first decoding circuit and adapted to generate driving signals for said memory cell access signal lines depending at least in part on said decoding and selecting signals.
摘要翻译：一种包括多个存储单元的存储器件，所述存储器单元被分组在至少两个存储器扇区中。在每个存储器扇区中，存储器单元根据存储单元的多个对准排列。相应的存储单元访问信号线与每个对准相关联。第一解码电路适于接收存储器单元的地址代码，并且响应于此，断言所述至少两个存储器扇区公用的多个解码和选择信号。与至少两个存储器扇区中的每一个相关联的相应的第二解码电路可操作地耦合到第一解码电路，并且适于至少部分地基于所述解码和选择信号来产生用于所述存储器单元存取信号线的驱动信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式