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1. 发明授权

US07136039B2 Method and related apparatus for driving an LCD monitor 有权
公开(公告)号：US07136039B2
公开(公告)日：2006-11-14
申请号：US10065665
申请日：2002-11-07
申请人： Lin-Kai Bu , Chin-Feng Cheng , Tsung-Yu Wu , Chuan-Cheng Hsiao
发明人： Lin-Kai Bu , Chin-Feng Cheng , Tsung-Yu Wu , Chuan-Cheng Hsiao
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3685 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2320/0233 , G09G2320/0276 , G09G2330/021
摘要： A method for driving an LCD monitor is disclosed. The LCD monitor includes a voltage selection unit used for outputting a plurality of driving voltages according to display data, and a plurality of output buffers each electrically connected to the voltage selection circuit and a corresponding pixel. In the beginning, an output port of each output buffer approaches voltage at an input port. Then, the output ports of the driving units, which approach the same input voltage, are electrically connected to have an average voltage. In addition, the LCD monitor further includes a timing controller for controlling operation of the output buffers. When output ports of the output buffers, which approach the same input voltage, are electrically connected, the output buffers are turned off for saving power.

2. 发明授权

US06806515B2 Layout of a decoder and the method thereof 失效
标题翻译：解码器的布局及其方法
公开(公告)号：US06806515B2
公开(公告)日：2004-10-19
申请号：US10044950
申请日：2002-01-15
申请人： Chuan-Cheng Hsiao , Lin-Kai Bu , Kun-Cheng Hung , Chien-Pin Chen
发明人： Chuan-Cheng Hsiao , Lin-Kai Bu , Kun-Cheng Hung , Chien-Pin Chen
IPC分类号： H01L31072
CPC分类号： H01L27/0207 , G02F1/1368 , G09G3/3688 , G09G2310/027
摘要： A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.
摘要翻译：提供具有m * n个节点的解码器的布局结构及其方法。节点包括多个晶体管节点和多个信道节点。晶体管节点的制造方法包括形成栅极，第一源极/漏极区域和第二源极/漏极区域。通道节点通过形成通道来制造。通道，第一源极/漏极区域和第二源极/漏极区域同时用相同的材料形成。具有较小宽度的解码器电路在本发明中实现而不需要额外的掩模。

3. 发明授权

US07081877B2 Apparatus and method for data signal scattering conversion 失效
公开(公告)号：US07081877B2
公开(公告)日：2006-07-25
申请号：US10121660
申请日：2002-04-15
申请人： Lin-Kai Bu , Chuan-Cheng Hsiao
发明人： Lin-Kai Bu , Chuan-Cheng Hsiao
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2310/027 , G09G2310/0297 , G09G2320/0233
摘要： An apparatus and a method for data signal scattering conversion. The apparatus includes a scattering multiplexer, a digital-to-analog converter, and a scattering demultiplexer. The scattering multiplexer is for receiving p digital data signals and outputting the q-th digital data signal of the p digital data signals. The digital-to-analog converter is to perform digital-to-analog conversion of the q-th digital data signal and output an analog data signal. The scattering demultiplexer has p output terminals, and is used for outputting the analog data signal through the q-th output terminal. Offset voltages output from the digital-to-analog converter are scattered over a number of data lines so that undesired points with abnormally deep or light colors due to the output offset voltages, are difficult to perceive.

4. 发明授权

US06956554B2 Apparatus for switching output voltage signals 失效
标题翻译：用于切换输出电压信号的装置
公开(公告)号：US06956554B2
公开(公告)日：2005-10-18
申请号：US10212077
申请日：2002-08-06
申请人： Yen-Chen Chen , Chien-Pin Chen , Chuan-Cheng Hsiao , Lin-Kai Bu , Kun-Cheng Hung
发明人： Yen-Chen Chen , Chien-Pin Chen , Chuan-Cheng Hsiao , Lin-Kai Bu , Kun-Cheng Hung
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , G09G2320/0276
摘要： An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.
摘要翻译：用于切换输出电压信号的装置包括电阻串，用于传递多个伽马电压输入信号的第一开关装置，用于传送高电压输入信号和低电压输入信号的第二开关装置，以及开关选择耦合到第一开关装置组和第二开关装置组的装置。当开关选择装置输出第一信号时，第一开关装置可将伽马电压输入信号传送到电阻串; 当开关选择装置输出第二信号时，第二开关装置将高压输入信号和低电压输入信号传送到电阻串。

5. 发明授权

US07184016B2 Data driver for an LCD panel 失效
标题翻译： LCD面板的数据驱动程序
公开(公告)号：US07184016B2
公开(公告)日：2007-02-27
申请号：US10668983
申请日：2003-09-22
申请人： Lin-Kai Bu , Chuan-Cheng Hsiao , Yen-Chen Chen
发明人： Lin-Kai Bu , Chuan-Cheng Hsiao , Yen-Chen Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027
摘要： A data driver for driving multiple data lines on an LCD panel according to multiple channels of pixel data. In the data driver, a digital buffer receives and stores the pixel data at several times and selectively outputs a channel of the pixel data at a time. A DAC receives the pixel data output from the digital buffer at several times, converts the pixel data into multiple channels of analog pixel data and outputs the analog pixel data at several times. An analog buffer receives the analog pixel data output from the DAC at several times and outputs the analog pixel data at a time. An output buffer receives the analog pixel data output from the analog buffer so as to drive the data lines.
摘要翻译：一种用于根据多个像素数据通道在LCD面板上驱动多条数据线的数据驱动器。在数据驱动器中，数字缓冲器多次接收并存储像素数据，并且一次选择性地输出像素数据的通道。 DAC从数字缓冲器中多次接收输出的像素数据，将像素数据转换为多通道的模拟像素数据，并多次输出模拟像素数据。模拟缓冲器多次接收从DAC输出的模拟像素数据，并一次输出模拟像素数据。输出缓冲器接收从模拟缓冲器输出的模拟像素数据，以驱动数据线。

6. 发明授权

US07612589B2 Phase-locked loop and control method utilizing the same 有权
标题翻译：锁相环及其控制方法
公开(公告)号：US07612589B2
公开(公告)日：2009-11-03
申请号：US11871223
申请日：2007-10-12
申请人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
发明人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/10 , H03L2207/06
摘要： A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.
摘要翻译：锁相环包括处理单元，压控振荡器和控制单元。处理单元根据参考时钟和第一反馈时钟之间的相位差，向节点生成控制电压。压控振荡器根据节点的电压产生第一反馈时钟。控制单元停用压控振荡器，并以断电模式向节点提供启动电压，并且启动压控振荡器以根据在加电模式下的节点的电压产生第一反馈时钟。控制单元在通电模式下停止提供启动电压。

7. 发明授权

US07272673B2 Signal generating circuit capable of generating a validation signal and related method thereof 有权
标题翻译：能产生验证信号的信号发生电路及其相关方法
公开(公告)号：US07272673B2
公开(公告)日：2007-09-18
申请号：US11163899
申请日：2005-11-03
申请人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
发明人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.
摘要翻译：用于产生确认信号的信号发生系统包括：用于将输出时钟锁定到特定时钟频率的锁相环（PLL）; 和数字信号发生电路。数字信号发生电路包括：电耦合到PLL的用于确定PLL的输出时钟是否在频率范围内的触发电路，以及如果输出时钟在频率范围内则输出触发信号; 以及信号发生装置，电耦合到所述触发电路和所述PLL，用于当接收到所述触发信号时根据所述输出时钟产生所述有效信号; 其中在输出时钟处于频率范围之前，PLL连续输出输出时钟。

8. 发明授权

US07123072B2 High-accuracy capacitor digital-to-analog converter 有权
标题翻译：高精度电容数模转换器
公开(公告)号：US07123072B2
公开(公告)日：2006-10-17
申请号：US10128663
申请日：2002-04-23
申请人： Linkai Bu , Chuan-Cheng Hsiao , Kun-Cheng Hung , Chien-Pin Chen
发明人： Linkai Bu , Chuan-Cheng Hsiao , Kun-Cheng Hung , Chien-Pin Chen
IPC分类号： G06G7/18
CPC分类号： H03M1/804
摘要： A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.
摘要翻译：用于N位数模转换的电容器数模转换器包括一个包括2个N电容器和2个N + 1个MOS开关的转换器电容器网络，以及一个输出缓冲区。 MOS开关在其各自的源极/漏极处以串联的方式连接，并且每个电容器具有连接到串联链中的两个连续的MOS开关之间的对应连接节点的第一电极和连接到公共节点的第二电极。输出缓冲器包括差分放大器和输出放大器，差分放大器具有两个离散输入端，每个离散输入端连接到转换器电容器网络中的电容器的对应的一个第一电极。

9. 发明授权

US07830005B2 Bond pad array for complex IC 有权
标题翻译：复合IC焊盘阵列
公开(公告)号：US07830005B2
公开(公告)日：2010-11-09
申请号：US12269814
申请日：2008-11-12
申请人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
发明人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06153 , H01L2224/85399 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.
摘要翻译：集成电路包括：基板; 和衬底上的接合焊盘阵列。接合焊盘阵列包括：一排内部接合焊盘，每个内部接合焊盘相对于多个内部焊盘开口定位; 多个第一内部金属层，分别耦合到内部接合焊盘，用于在内部焊盘和内部电路之间传输信号，其中至少一个第一内部金属层的宽度小于相应的内部接合焊盘的宽度; 一排外接合焊盘，相对于一排内部接合焊盘交错排列; 以及多个第一外金属层，其分别耦合到外接合焊盘，用于在外焊盘和内部电路之间传输信号，其中至少一个内焊盘与第一外金属层相邻重叠。

10. 发明授权

US07796719B2 Signal detection apparatus and method thereof 有权
标题翻译：信号检测装置及其方法
公开(公告)号：US07796719B2
公开(公告)日：2010-09-14
申请号：US11125475
申请日：2005-05-10
申请人： Chuan Liu , Chuan-Cheng Hsiao , Pao-Ching Tseng
发明人： Chuan Liu , Chuan-Cheng Hsiao , Pao-Ching Tseng
IPC分类号： H03D3/24
CPC分类号： G06F13/385
摘要： The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated clock generation device generates a sampling clock signal according to a predetermined clock signal. The signal processor generates a plurality of detection results based on the sampling clock signal and the input signal. The logic determination device receives the plural of detection results and determines whether the input signal is the OOB signal.
摘要翻译：本发明公开了一种用于检测一组串行ATA信号的输入信号是否为带外（OOB）信号的信号检测装置及其方法。信号检测装置包括校准时钟产生装置，信号处理器和逻辑判定装置。校准时钟产生装置根据预定的时钟信号产生采样时钟信号。信号处理器基于采样时钟信号和输入信号产生多个检测结果。逻辑判定装置接收多个检测结果，并判断输入信号是否为OOB信号。

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