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1. 发明申请

US20100117207A1 BOND PAD ARRAY FOR COMPLEX IC 有权
标题翻译：复合IC的BOND PAD ARRAY
公开(公告)号：US20100117207A1
公开(公告)日：2010-05-13
申请号：US12269814
申请日：2008-11-12
申请人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
发明人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06153 , H01L2224/85399 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.
摘要翻译：集成电路包括：基板; 和衬底上的接合焊盘阵列。接合焊盘阵列包括：一排内部接合焊盘，每个内部接合焊盘相对于多个内部焊盘开口定位; 多个第一内部金属层，分别耦合到内部接合焊盘，用于在内部焊盘和内部电路之间传输信号，其中至少一个第一内部金属层的宽度小于相应的内部接合焊盘的宽度; 一排外接合焊盘，相对于一排内部接合焊盘交错排列; 以及多个第一外金属层，其分别耦合到外接合焊盘，用于在外焊盘和内部电路之间传输信号，其中至少一个内焊盘与第一外金属层相邻重叠。

2. 发明授权

US07830005B2 Bond pad array for complex IC 有权
标题翻译：复合IC焊盘阵列
公开(公告)号：US07830005B2
公开(公告)日：2010-11-09
申请号：US12269814
申请日：2008-11-12
申请人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
发明人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06153 , H01L2224/85399 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.
摘要翻译：集成电路包括：基板; 和衬底上的接合焊盘阵列。接合焊盘阵列包括：一排内部接合焊盘，每个内部接合焊盘相对于多个内部焊盘开口定位; 多个第一内部金属层，分别耦合到内部接合焊盘，用于在内部焊盘和内部电路之间传输信号，其中至少一个第一内部金属层的宽度小于相应的内部接合焊盘的宽度; 一排外接合焊盘，相对于一排内部接合焊盘交错排列; 以及多个第一外金属层，其分别耦合到外接合焊盘，用于在外焊盘和内部电路之间传输信号，其中至少一个内焊盘与第一外金属层相邻重叠。

3. 发明授权

US08525310B2 Leadframe package for high-speed data rate applications 有权
标题翻译：用于高速数据速率应用的引线框封装
公开(公告)号：US08525310B2
公开(公告)日：2013-09-03
申请号：US13085446
申请日：2011-04-12
申请人： Nan-Jang Chen , Chun-Wei Chang , Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li , Nan-Cheng Chen
发明人： Nan-Jang Chen , Chun-Wei Chang , Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li , Nan-Cheng Chen
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L23/49503 , H01L23/49541 , H01L23/49551 , H01L24/48 , H01L2224/05554 , H01L2224/48177 , H01L2224/48247 , H01L2224/49109 , H01L2224/49175 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.
摘要翻译：半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

4. 发明授权

US08050129B2 E-fuse apparatus for controlling reference voltage required for programming/reading e-fuse macro in an integrated circuit via switch device in the same integrated circuit 有权
标题翻译：用于控制在同一集成电路中通过开关装置在集成电路中编程/读取电容保险丝宏需要的参考电压的电熔丝装置
公开(公告)号：US08050129B2
公开(公告)日：2011-11-01
申请号：US12491247
申请日：2009-06-25
申请人： Chia-Hsien Liu , Rei-Fu Huang , Chien-Chung Chen , Che-Yuan Jao
发明人： Chia-Hsien Liu , Rei-Fu Huang , Chien-Chung Chen , Che-Yuan Jao
IPC分类号： G11C7/00
CPC分类号： G04B37/0481 , G04B19/065
摘要： An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.
摘要翻译：电可编程保险丝（e-fuse）装置包括电子熔丝宏和开关装置。电子熔丝宏设置在集成电路中，并且具有多个电子熔丝单元。开关装置设置在集成电路中，并且具有耦合到电子熔丝单元的输出节点和耦合到第一电源的第一输入节点，第一电源提供充当电子熔丝宏的编程电压的第一参考电压。当在编程模式下操作电子熔丝宏时，开关装置将第一电源连接到电子熔丝单元。

5. 发明申请

US20090184395A1 INPUT/OUTPUT (I/O) BUFFER 审中-公开
标题翻译：输入/输出（I / O）缓冲器
公开(公告)号：US20090184395A1
公开(公告)日：2009-07-23
申请号：US12018206
申请日：2008-01-23
申请人： Che-Yuan Jao
发明人： Che-Yuan Jao
IPC分类号： H01L29/86 , H02H3/08
CPC分类号： H01L27/0288
摘要： An I/O buffer including an I/O circuit, a pad and a pulling resistant device. The I/O circuit is for inputting or outputting a signal. The pulling resistant device has a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value.
摘要翻译： I / O缓冲器包括I / O电路，焊盘和抗拉装置。 I / O电路用于输入或输出信号。抗拉装置具有电连接在I / O电路和焊盘之间的多个电阻元件，用于形成电阻值。

6. 发明授权

US08692605B2 Receiving circuits for core circuits 有权
标题翻译：核心电路接收电路
公开(公告)号：US08692605B2
公开(公告)日：2014-04-08
申请号：US13169467
申请日：2011-06-27
申请人： Che-Yuan Jao
发明人： Che-Yuan Jao
IPC分类号： H03K5/08 , H03K19/00
CPC分类号： H03K19/00 , H03K5/08 , H03K5/2472
摘要： A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.
摘要翻译：提供了一种用于核心电路的接收电路，并且包括第一接收路径单元。第一接收路径单元能够接收输入信号，并根据输入信号向核心电路输出输出信号。第一接收路径单元包括能够在核心电路的核心电源域中操作并接收第一钳位信号的输入缓冲器。当输入信号的电平基本上等于或低于第一预定电压电平时，输入信号被传递到输入缓冲器以用作第一钳位信号，并且输入缓冲器能够输出输出信号核心电源域根据第一个钳位信号。当输入信号的电平高于第一预定电压电平时，输入信号不会传递到输入缓冲器。

7. 发明授权

US08258615B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08258615B2
公开(公告)日：2012-09-04
申请号：US12389388
申请日：2009-02-20
申请人： Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li
发明人： Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li
IPC分类号： H01L23/498
CPC分类号： H01L23/642 , H01L23/3114 , H01L23/367 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/73215 , H01L2924/00014 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.
摘要翻译：本发明提供能够消除半导体器件内的半导体管芯的电压（IR）下降的半导体器件以及半导体器件的制造方法。半导体器件包括半导体管芯，并且半导体管芯包括第一表面区域，潜在地相当于彼此的多个第一焊盘，钝化层，多个第一开口和第一导电介质层。钝化层设置在多个第一焊盘上。多个第一开口形成在钝化层上，并用于暴露多个第一焊盘。第一导电介质层形成在第一表面区域上，用于实现多个第一开口以连接多个第一焊盘。

8. 发明申请

US20100171211A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100171211A1
公开(公告)日：2010-07-08
申请号：US12350208
申请日：2009-01-07
申请人： Che-Yuan Jao , Sheng-Ming Chang
发明人： Che-Yuan Jao , Sheng-Ming Chang
IPC分类号： H01L23/488
CPC分类号： H01L24/06 , H01L23/50 , H01L23/552 , H01L24/05 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05599 , H01L2224/32145 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48139 , H01L2224/48145 , H01L2224/48147 , H01L2224/48463 , H01L2224/4847 , H01L2224/4911 , H01L2224/49111 , H01L2224/85399 , H01L2225/06506 , H01L2225/06527 , H01L2924/00014 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01076 , H01L2924/01077 , H01L2924/01082 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is provided by the present invention. The semiconductor device includes a semiconductor die, and the semiconductor die includes a die core having at least two bond pads with voltage level equivalent to each other and electrically connected to each other via at least a bond wire, and an input/output (I/O) periphery. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.
摘要翻译：本发明提供一种半导体器件。所述半导体器件包括半导体管芯，并且所述半导体管芯包括具有至少两个接合焊盘的芯片，所述至少两个接合焊盘的电压水平彼此相等并且至少通过接合线彼此电连接，以及输入/输出（I / O）周边。本发明的半导体器件能够以低成本解决半导体管芯的IR下降。

9. 发明申请

US20120326753A1 RECEIVING CIRCUITS FOR CORE CIRCUITS 有权
标题翻译：接收核心电路电路
公开(公告)号：US20120326753A1
公开(公告)日：2012-12-27
申请号：US13169467
申请日：2011-06-27
申请人： Che-Yuan Jao
发明人： Che-Yuan Jao
IPC分类号： H03K5/22
CPC分类号： H03K19/00 , H03K5/08 , H03K5/2472
摘要： A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.
摘要翻译：提供了一种用于核心电路的接收电路，并且包括第一接收路径单元。第一接收路径单元能够接收输入信号，并根据输入信号向核心电路输出输出信号。第一接收路径单元包括能够在核心电路的核心电源域中操作并接收第一钳位信号的输入缓冲器。当输入信号的电平基本上等于或低于第一预定电压电平时，输入信号被传递到输入缓冲器以用作第一钳位信号，并且输入缓冲器能够输出输出信号核心电源域根据第一个钳位信号。当输入信号的电平高于第一预定电压电平时，输入信号不会传递到输入缓冲器。

10. 发明申请

US20110248394A1 LEADFRAME PACKAGE FOR HIGH-SPEED DATA RATE APPLICATIONS 有权
标题翻译： LEADFRAME包用于高速数据速率应用
公开(公告)号：US20110248394A1
公开(公告)日：2011-10-13
申请号：US13085446
申请日：2011-04-12
申请人： Nan-Jang Chen , Chun-Wei Chang , Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li , Nan-Cheng Chen
发明人： Nan-Jang Chen , Chun-Wei Chang , Sheng-Ming Chang , Che-Yuan Jao , Ching-Chih Li , Nan-Cheng Chen
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L23/49503 , H01L23/49541 , H01L23/49551 , H01L24/48 , H01L2224/05554 , H01L2224/48177 , H01L2224/48247 , H01L2224/49109 , H01L2224/49175 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.
摘要翻译：半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

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