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1. 发明申请

US20100117207A1 BOND PAD ARRAY FOR COMPLEX IC 有权
标题翻译：复合IC的BOND PAD ARRAY
公开(公告)号：US20100117207A1
公开(公告)日：2010-05-13
申请号：US12269814
申请日：2008-11-12
申请人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
发明人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06153 , H01L2224/85399 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.
摘要翻译：集成电路包括：基板; 和衬底上的接合焊盘阵列。接合焊盘阵列包括：一排内部接合焊盘，每个内部接合焊盘相对于多个内部焊盘开口定位; 多个第一内部金属层，分别耦合到内部接合焊盘，用于在内部焊盘和内部电路之间传输信号，其中至少一个第一内部金属层的宽度小于相应的内部接合焊盘的宽度; 一排外接合焊盘，相对于一排内部接合焊盘交错排列; 以及多个第一外金属层，其分别耦合到外接合焊盘，用于在外焊盘和内部电路之间传输信号，其中至少一个内焊盘与第一外金属层相邻重叠。

2. 发明授权

US07830005B2 Bond pad array for complex IC 有权
标题翻译：复合IC焊盘阵列
公开(公告)号：US07830005B2
公开(公告)日：2010-11-09
申请号：US12269814
申请日：2008-11-12
申请人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
发明人： Chuan-Cheng Hsiao , Hung-Sung Li , I-Cheng Lin , Che-Yuan Jao
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06153 , H01L2224/85399 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.
摘要翻译：集成电路包括：基板; 和衬底上的接合焊盘阵列。接合焊盘阵列包括：一排内部接合焊盘，每个内部接合焊盘相对于多个内部焊盘开口定位; 多个第一内部金属层，分别耦合到内部接合焊盘，用于在内部焊盘和内部电路之间传输信号，其中至少一个第一内部金属层的宽度小于相应的内部接合焊盘的宽度; 一排外接合焊盘，相对于一排内部接合焊盘交错排列; 以及多个第一外金属层，其分别耦合到外接合焊盘，用于在外焊盘和内部电路之间传输信号，其中至少一个内焊盘与第一外金属层相邻重叠。

3. 发明授权

US08208233B2 ESD protection circuit and method thereof 有权
标题翻译： ESD保护电路及其方法
公开(公告)号：US08208233B2
公开(公告)日：2012-06-26
申请号：US12050175
申请日：2008-03-18
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： The present invention provides an ESD protection circuit, including: a first protecting circuit coupled between a first pad and a second pad, the first protecting circuit including a first discharge transistor; and a second protecting circuit coupled to the first pad and the second pad, the second protecting circuit including a second discharge transistor. One of the first and second discharge transistors is a high-voltage component, and the other of the first and second discharge transistors is a low-voltage component.
摘要翻译：本发明提供一种ESD保护电路，包括：耦合在第一焊盘和第二焊盘之间的第一保护电路，所述第一保护电路包括第一放电晶体管; 以及耦合到所述第一焊盘和所述第二焊盘的第二保护电路，所述第二保护电路包括第二放电晶体管。第一和第二放电晶体管中的一个是高电压分量，第一和第二放电晶体管中的另一个是低电压分量。

4. 发明授权

US07221027B2 Latchup prevention method for integrated circuits and device using the same 有权
标题翻译：集成电路的防抱死方法及其使用的装置
公开(公告)号：US07221027B2
公开(公告)日：2007-05-22
申请号：US10847317
申请日：2004-05-18
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： H02H9/00
CPC分类号： H01L27/0255 , H01L27/0629 , H01L27/0921
摘要： An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first current shunting diode has an anode coupled to the pad and a cathode coupled to a first voltage source. A second current shunting diode has a cathode coupled to the pad and an anode coupled to a second voltage source. Minority-carriers guard rings surround the first current shunting diode and the second shunting diode. Distance between the first and second current shunting diodes and the internal circuit, the active area and the ESD protection circuit exceed 80 μm.
摘要翻译：集成电路防止闭锁。在集成电路中，内部电路设置在衬底中并具有寄生SCR结构。至少一个ESD保护电路和有源区域设置在衬底上并且耦合到衬垫。第一电流分流二极管具有耦合到焊盘的阳极和耦合到第一电压源的阴极。第二电流分流二极管具有耦合到焊盘的阴极和耦合到第二电压源的阳极。少数载波保护环围绕第一电流分流二极管和第二分流二极管。第一和第二电流分流二极管与内部电路，有源区和ESD保护电路之间的距离超过80 mum。

5. 发明授权

US06988701B1 Flag or post support device 失效
标题翻译：标记或后支持设备
公开(公告)号：US06988701B1
公开(公告)日：2006-01-24
申请号：US10911350
申请日：2004-08-05
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： F16M13/00
CPC分类号： G09F17/00 , F16C11/045 , F16C11/10 , F16M11/08 , F16M11/10 , F16M13/02 , F16M2200/024
摘要： A flag or post support device includes a base having a bottom plate for securing to supporting surfaces, two flaps extended from the bottom plate and each having a number of teeth formed around an orifice, a seat rotatably received between the flaps and having two blocks rotatably secured to the flaps with a fastener, each of the blocks includes a number of teeth for engaging with the teeth of the flaps, and for adjustably securing the blocks of the seat to the base at selected angular positions. A post includes one end received in the seat, and has a passage to receive the fastener, and to solidly secure the post to the seat and thus to the base, and to prevent the post from being disengaged from the seat and the base.
摘要翻译：标志或后支撑装置包括具有用于固定到支撑表面的底板的基部，从底板延伸的两个翼片，并且每个具有围绕孔形成的多个齿;座椅，可旋转地容纳在翼片之间，并且具有可旋转的两个块通过紧固件固定到翼片上，每个块包括用于与翼片的齿接合的多个齿，并且用于在选定的角度位置可调节地将座椅的块固定到基座。支柱包括容纳在座椅中的一端，并且具有用于接收紧固件的通道，并且将柱牢固地固定到座椅上并因此固定到基座，并且防止柱子从座椅和基座脱离。

6. 发明申请

US20100123984A1 ESD PROTECTION CIRCUIT AND CIRCUITRY OF IC APPLYING THE ESD PROTECTION CIRCUIT 有权
标题翻译：应用ESD保护电路的IC的ESD保护电路和电路
公开(公告)号：US20100123984A1
公开(公告)日：2010-05-20
申请号：US12271052
申请日：2008-11-14
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： H02H9/00
CPC分类号： H01L27/0288 , H01L27/0251
摘要： A circuitry of an IC is provided, including a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path.
摘要翻译：提供IC的电路，包括焊盘，内部电路和ESD保护电路。垫片发送或接收信号并耦合到第一节点。内部电路耦合到第一节点处理信号。 ESD保护电路包括ESD钳位电路，第一限流和分流单元以及第二限流和分流单元。 ESD钳位电路耦合到第一节点，用于钳位流经第一节点的ESD电流。第一电流限制和分流单元通过耦合到焊盘的第一节点，用于限制ESD电流并将ESD电流的一部分分流到第一电压路径。第二电流限制和分流单元耦合到第一限流和分流单元，用于限制ESD电流并将ESD电流的一部分分流到第二电压路径。

7. 发明申请

US20060027725A1 FLAG OR POST SUPPORT DEVICE 失效
标题翻译：标志或支持设备
公开(公告)号：US20060027725A1
公开(公告)日：2006-02-09
申请号：US10911350
申请日：2004-08-05
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： G09F19/00 , H01Q1/12
CPC分类号： G09F17/00 , F16C11/045 , F16C11/10 , F16M11/08 , F16M11/10 , F16M13/02 , F16M2200/024
摘要： A flag or post support device includes a base having a bottom plate for securing to supporting surfaces, two flaps extended from the bottom plate and each having a number of teeth formed around an orifice, a seat rotatably received between the flaps and having two blocks rotatably secured to the flaps with a fastener, each of the blocks includes a number of teeth for engaging with the teeth of the flaps, and for adjustably securing the blocks of the seat to the base at selected angular positions. A post includes one end received in the seat, and has a passage to receive the fastener, and to solidly secure the post to the seat and thus to the base, and to prevent the post from being disengaged from the seat and the base.
摘要翻译：标志或后支撑装置包括具有用于固定到支撑表面的底板的基部，从底板延伸的两个翼片，并且每个具有围绕孔形成的多个齿;座椅，可旋转地容纳在翼片之间，并且具有可旋转的两个块通过紧固件固定到翼片上，每个块包括用于与翼片的齿接合的多个齿，并且用于在选定的角度位置可调节地将座椅的块固定到基座。支柱包括容纳在座椅中的一端，并且具有用于接收紧固件的通道，并且将柱牢固地固定到座椅上并因此固定到基座，并且防止柱子从座椅和基座脱离。

8. 发明申请

US20050259372A1 Latchup prevention method for integrated circuits and device using the same 有权
标题翻译：集成电路的防抱死方法及其使用的装置
公开(公告)号：US20050259372A1
公开(公告)日：2005-11-24
申请号：US10847317
申请日：2004-05-18
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H02H9/00
CPC分类号： H01L27/0255 , H01L27/0629 , H01L27/0921
摘要： An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first current shunting diode has an anode coupled to the pad and a cathode coupled to a first voltage source. A second current shunting diode has a cathode coupled to the pad and an anode coupled to a second voltage source. Minority-carriers guard rings surround the first current shunting diode and the second shunting diode. Distance between the first and second current shunting diodes and the internal circuit, the active area and the ESD protection circuit exceed 80 μm.
摘要翻译：集成电路防止闭锁。在集成电路中，内部电路设置在衬底中并具有寄生SCR结构。至少一个ESD保护电路和有源区域设置在衬底上并且耦合到衬垫。第一电流分流二极管具有耦合到焊盘的阳极和耦合到第一电压源的阴极。第二电流分流二极管具有耦合到焊盘的阴极和耦合到第二电压源的阳极。少数载波保护环围绕第一电流分流二极管和第二分流二极管。第一和第二电流分流二极管与内部电路，有源区和ESD保护电路之间的距离超过80 mum。

9. 发明申请

US20100061026A1 ESD PROTECTION CIRCUIT AND METHOD THEREOF 有权
标题翻译： ESD保护电路及其方法
公开(公告)号：US20100061026A1
公开(公告)日：2010-03-11
申请号：US12206748
申请日：2008-09-09
申请人： I-Cheng Lin , Tao Cheng
发明人： I-Cheng Lin , Tao Cheng
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H02H3/006
摘要： An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.
摘要翻译：一种静电放电保护电路，电路包括瞬态检测电路，电平调节电路，放电电路和维持电路。瞬态检测电路耦合到第一焊盘，用于检测第一焊盘处的输入信号以产生瞬态信号; 电平调节电路耦合到瞬态检测电路，用于调整电平调节电路的输出端的输出电压; 放电电路耦合到电平调节电路的第一焊盘和输出端，用于当由输出电压使能时将第一焊盘的输入信号放电到第二焊盘; 并且所述维持电路耦合在所述电平调整电路和所述瞬态检测电路之间，用于选择性地控制所述电平调整电路，以根据所述瞬态信号维持所述放电电路的使能。

10. 发明申请

US20090237846A1 ESD PROTECTION CIRCUIT AND METHOD THEREOF 有权
标题翻译： ESD保护电路及其方法
公开(公告)号：US20090237846A1
公开(公告)日：2009-09-24
申请号：US12050175
申请日：2008-03-18
申请人： I-Cheng Lin
发明人： I-Cheng Lin
IPC分类号： H02H9/00 , H01L21/8234
CPC分类号： H02H9/046
摘要： The present invention provides an ESD protection circuit, including: a first protecting circuit coupled between a first pad and a second pad, the first protecting circuit including a first discharge transistor; and a second protecting circuit coupled to the first pad and the second pad, the second protecting circuit including a second discharge transistor. One of the first and second discharge transistors is a high-voltage component, and the other of the first and second discharge transistors is a low-voltage component.
摘要翻译：本发明提供一种ESD保护电路，包括：耦合在第一焊盘和第二焊盘之间的第一保护电路，所述第一保护电路包括第一放电晶体管; 以及耦合到所述第一焊盘和所述第二焊盘的第二保护电路，所述第二保护电路包括第二放电晶体管。第一和第二放电晶体管中的一个是高电压分量，第一和第二放电晶体管中的另一个是低电压分量。

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