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1. 发明申请

US20140047223A1 SELECTIVELY ACTIVATING A RESUME CHECK OPERATION IN A MULTI-THREADED PROCESSING SYSTEM 有权
标题翻译：选择性地激活多线程处理系统中的恢复检查操作
公开(公告)号：US20140047223A1
公开(公告)日：2014-02-13
申请号：US13624657
申请日：2012-09-21
申请人： Lin Chen , Yun Du , Andrew Gruber
发明人： Lin Chen , Yun Du , Andrew Gruber
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3885 , G06F9/3887
摘要： This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether a resume check operation is to be performed for the instruction. A compiler is also described that is configured to generate compiled code which, when executed, causes a resume check operation to be selectively enabled or disabled for particular instructions. The compiled code may include one or more instructions that each specify whether a resume check operation is to be performed for the respective instruction. The techniques of this disclosure may be used to reduce the power consumption of and/or improve the performance of a SIMD system that utilizes a resume check operation to manage the reactivation of deactivated threads.
摘要翻译：本公开描述了用于在单个指令，多数据（SIMD）处理系统中选择性地激活恢复检查操作的技术。描述了一种处理器，其被配置为基于指示是否对该指令执行恢复检查操作的指令中的信息选择性地启用或禁用特定指令的恢复检查操作。还描述了一种编译器，其被配置为生成编译代码，其在被执行时导致对特定指令选择性地启用或禁用恢复检查操作。编译代码可以包括一个或多个指令，每个指令指定是否对相应的指令执行恢复检查操作。本公开的技术可以用于减少利用恢复检查操作来管理停用线程的重新激活的SIMD系统的功耗和/或提高性能。

2. 发明授权

US09256429B2 Selectively activating a resume check operation in a multi-threaded processing system 有权
标题翻译：在多线程处理系统中选择性地激活恢复检查操作
公开(公告)号：US09256429B2
公开(公告)日：2016-02-09
申请号：US13624657
申请日：2012-09-21
申请人： Lin Chen , Yun Du , Andrew Gruber
发明人： Lin Chen , Yun Du , Andrew Gruber
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30072 , G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3885 , G06F9/3887
摘要： This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether a resume check operation is to be performed for the instruction. A compiler is also described that is configured to generate compiled code which, when executed, causes a resume check operation to be selectively enabled or disabled for particular instructions. The compiled code may include one or more instructions that each specify whether a resume check operation is to be performed for the respective instruction. The techniques of this disclosure may be used to reduce the power consumption of and/or improve the performance of a SIMD system that utilizes a resume check operation to manage the reactivation of deactivated threads.
摘要翻译：本公开描述了用于在单个指令，多数据（SIMD）处理系统中选择性地激活恢复检查操作的技术。描述了一种处理器，其被配置为基于指示是否对该指令执行恢复检查操作的指令中的信息选择性地启用或禁用特定指令的恢复检查操作。还描述了一种编译器，其被配置为生成编译代码，其在被执行时导致对特定指令选择性地启用或禁用恢复检查操作。编译代码可以包括一个或多个指令，每个指令指定是否对相应的指令执行恢复检查操作。本公开的技术可以用于减少利用恢复检查操作来管理停用线程的重新激活的SIMD系统的功耗和/或提高性能。

3. 发明授权

US08355028B2 Scheme for varying packing and linking in graphics systems 有权
标题翻译：在图形系统中改变包装和链接的方案
公开(公告)号：US08355028B2
公开(公告)日：2013-01-15
申请号：US11830667
申请日：2007-07-30
申请人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

4. 发明申请

US20090265528A1 PROGRAMMABLE STREAMING PROCESSOR WITH MIXED PRECISION INSTRUCTION EXECUTION 有权
标题翻译：具有混合精度指令执行的可编程流水处理器
公开(公告)号：US20090265528A1
公开(公告)日：2009-10-22
申请号：US12106654
申请日：2008-04-21
申请人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
发明人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
IPC分类号： G06F9/30
CPC分类号： G06T15/005 , G06F8/47
摘要： The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision. The controller then causes the selected execution unit to execute the instruction with the indicated data precision using the graphics data associated with the instruction.
摘要翻译：本公开涉及一种能够使用不同执行单元执行混合精度（例如，全精度，半精度）指令的可编程流式处理器。各种执行单元都能够使用图形数据来执行特定精度级别的指令。示例性可编程着色器处理器包括控制器和多个执行单元。控制器被配置为接收用于执行的指令并且接收用于执行指令的数据精度的指示。控制器还被配置为接收单独的转换指令，该指令在执行时将与指令相关联的图形数据转换为所指示的数据精度。当可操作时，控制器基于指示的数据精度选择一个执行单元。然后，控制器使所选择的执行单元使用与指令相关联的图形数据，以指示的数据精度执行指令。

5. 发明申请

US20090113402A1 SERVER-BASED CODE COMPILATION 有权
标题翻译：基于服务器的代码编译
公开(公告)号：US20090113402A1
公开(公告)日：2009-04-30
申请号：US11925476
申请日：2007-10-26
申请人： Lingjun Chen , Guofang Jiao , Yun Du , Chun Yu
发明人： Lingjun Chen , Guofang Jiao , Yun Du , Chun Yu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： A server is disclosed that includes an interface to a data communication network, a compiler library that stores a plurality of different compilers, and compiler selection logic responsive to data received at the interface and including logic. The compiler selection logic is configured to select one of the plurality of different compilers based on an evaluation of the received data. The selected compiler generates compiled output data and the compiled output data is communicated over the data communication network to a client.
摘要翻译：公开了一种服务器，其包括对数据通信网络的接口，存储多个不同编译器的编译器库，以及响应于在接口处接收的数据并包括逻辑的编译器选择逻辑。编译器选择逻辑被配置为基于对接收到的数据的评估来选择多个不同编译器之一。所选择的编译器生成编译的输出数据，并且编译的输出数据通过数据通信网络传送到客户机。

6. 发明申请

US20090096797A1 DEMAND BASED POWER CONTROL IN A GRAPHICS PROCESSING UNIT 有权
标题翻译：图形处理单元中基于需求的功率控制
公开(公告)号：US20090096797A1
公开(公告)日：2009-04-16
申请号：US11870597
申请日：2007-10-11
申请人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
发明人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
IPC分类号： G06F15/80
CPC分类号： G06F1/3203 , G06F1/3287 , G06T1/20 , Y02D10/171 , Y02D50/20
摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.
摘要翻译：这里公开了与图形处理单元一起使用的功率控制器。功率控制器监视，管理和控制提供给图形处理单元的管线的组件的电力。功率控制器基于由电力控制器与流水线部件相关联的状态信息来确定是否以及在何种程度上向管道部件提供功率。功率控制器能够使用接收到的状态信息来识别趋势，并且基于所识别的趋势来确定是否以及在何种程度上向管道部件供电。

7. 发明申请

US20090033672A1 SCHEME FOR VARYING PACKING AND LINKING IN GRAPHICS SYSTEMS 有权
标题翻译：在图形系统中改变包装和连接的方案
公开(公告)号：US20090033672A1
公开(公告)日：2009-02-05
申请号：US11830667
申请日：2007-07-30
申请人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

8. 发明申请

US20080246773A1 INDEXES OF GRAPHICS PROCESSING OBJECTS IN GRAPHICS PROCESSING UNIT COMMANDS 有权
标题翻译：图形处理单元命令中图形处理对象的指标
公开(公告)号：US20080246773A1
公开(公告)日：2008-10-09
申请号：US11696665
申请日：2007-04-04
申请人： Guofang Jiao , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Lingjun Chen , Yun Du
IPC分类号： G06T1/00
CPC分类号： G06T15/00
摘要： This disclosure describes techniques of loading batch commands into a graphics processing unit (GPU). As described herein, a GPU driver for the GPU identifies one or more graphics processing objects to be used by the GPU in order to render a batch of graphics primitives. The GPU driver may insert indexes associated with the identified graphics processing objects into a batch command. The GPU driver may then issue the batch command to the GPU. The GPU may use the indexes in the batch command to retrieve the graphics processing objects from memory. After retrieving the graphics processing objects from memory, the GPU may use the graphics processing objects to render the batch of graphics primitives.
摘要翻译：本公开描述了将批处理命令加载到图形处理单元（GPU）中的技术。如本文所述，用于GPU的GPU驱动器识别要由GPU使用的一个或多个图形处理对象，以便呈现一批图形基元。 GPU驱动程序可以将与所识别的图形处理对象相关联的索引插入到批处理命令中。然后，GPU驱动程序可以向GPU发出批处理命令。 GPU可以使用批处理命令中的索引从内存中检索图形处理对象。在从存储器检索图形处理对象之后，GPU可以使用图形处理对象来渲染批量的图形基元。

9. 发明申请

US20080201716A1 ON-DEMAND MULTI-THREAD MULTIMEDIA PROCESSOR 有权
标题翻译：多用途多媒体处理器
公开(公告)号：US20080201716A1
公开(公告)日：2008-08-21
申请号：US11677362
申请日：2007-02-21
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46
CPC分类号： G06F12/0842 , G06F9/30145 , G06F9/30167 , G06F9/382 , G06F9/383 , G06F9/3851 , G06F9/3885 , G06F9/45558 , G06F9/5016 , G06F12/10 , G06F2009/45579 , G06F2009/45583 , Y02D10/13 , Y02D10/22
摘要： A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, data, and state information for the applications and assignable processing units to perform various types of processing for the applications. The configurable storage resources may include an instruction cache to store instructions for the applications, register banks to store data for the applications, context registers to store state information for threads of the applications, etc. The processing units may include an arithmetic logic unit (ALU) core, an elementary function core, a logic core, a texture sampler, a load control unit, a flow controller, etc. The multimedia processor allocates a configurable portion of the storage resources to each application and dynamically assigns the processing units to the applications as requested by these applications.
摘要翻译：一种设备包括多媒体处理器，其可以同时支持用于各种类型的多媒体（例如图形，音频，视频，照相机，游戏等）的多个应用。多媒体处理器包括可配置的存储资源以存储用于应用的指令，数据和状态信息以及可分配处理单元来执行用于应用的各种类型的处理。可配置的存储资源可以包括用于存储用于应用的指令的指令高速缓存，寄存器组存储用于应用的数据，上下文寄存器以存储用于应用的线程的状态信息等。处理单元可以包括算术逻辑单元（ALU ）核心，基本功能核心，逻辑核心，纹理采样器，负载控制单元，流量控制器等。多媒体处理器将存储资源的可配置部分分配给每个应用，并且将处理单元动态地分配给应用按照这些应用的要求。

10. 发明申请

US20080074430A1 GRAPHICS PROCESSING UNIT WITH UNIFIED VERTEX CACHE AND SHADER REGISTER FILE 有权
标题翻译：具有统一VERTEX CACHE和SHADER寄存器文件的图形处理单元
公开(公告)号：US20080074430A1
公开(公告)日：2008-03-27
申请号：US11535809
申请日：2006-09-27
申请人： Guofang Jiao , Chun Yu , Yun Du
发明人： Guofang Jiao , Chun Yu , Yun Du
IPC分类号： G06T1/00
CPC分类号： G06T15/005
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.
摘要翻译：描述了使用统一的顶点高速缓存和着色器寄存器文件处理具有图形处理单元（GPU）的计算机化图像的技术。这些技术包括创建耦合到GPU流水线的共享着色器和耦合到共享着色器的统一顶点高速缓存和着色器寄存器文件，以基本上消除GPU流水线内的数据移动。 GPU管道将基于图像的图像几何的图像几何信息发送到共享着色器。共享着色器执行顶点着色以生成图像中顶点坐标和顶点属性。共享着色器然后将顶点属性存储在统一的顶点缓存和着色器寄存器文件中，并且仅将顶点的顶点坐标发送回GPU管道。 GPU流水线基于顶点坐标处理图像，共享着色器基于顶点属性处理图像。

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