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1. 发明授权

US08355028B2 Scheme for varying packing and linking in graphics systems 有权
标题翻译：在图形系统中改变包装和链接的方案
公开(公告)号：US08355028B2
公开(公告)日：2013-01-15
申请号：US11830667
申请日：2007-07-30
申请人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

2. 发明申请

US20090033672A1 SCHEME FOR VARYING PACKING AND LINKING IN GRAPHICS SYSTEMS 有权
标题翻译：在图形系统中改变包装和连接的方案
公开(公告)号：US20090033672A1
公开(公告)日：2009-02-05
申请号：US11830667
申请日：2007-07-30
申请人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Alexei V. Bourd , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

3. 发明授权

US08884972B2 Graphics processor with arithmetic and elementary function units 有权
标题翻译：具有算术和基本功能单元的图形处理器
公开(公告)号：US08884972B2
公开(公告)日：2014-11-11
申请号：US11441696
申请日：2006-05-25
申请人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
发明人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
IPC分类号： G06F15/16 , G06F15/00 , G06T1/00 , G06F9/38 , G06F9/30
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

4. 发明申请

US20070273698A1 Graphics processor with arithmetic and elementary function units 有权
标题翻译：具有算术和基本功能单元的图形处理器
公开(公告)号：US20070273698A1
公开(公告)日：2007-11-29
申请号：US11441696
申请日：2006-05-25
申请人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
发明人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

5. 发明授权

US08760457B2 Data access tool for programmable graphics hardware 有权
标题翻译：可编程图形硬件的数据访问工具
公开(公告)号：US08760457B2
公开(公告)日：2014-06-24
申请号：US11782509
申请日：2007-07-24
申请人： Alexei V. Bourd , Guofang Jiao , Lin Chen
发明人： Alexei V. Bourd , Guofang Jiao , Lin Chen
IPC分类号： G09G5/39 , G06T1/00 , G06T15/00 , G06F15/16
CPC分类号： G06T15/005
摘要： Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user.
摘要翻译：提供了在可编程图形硬件内访问数据的方法和装置。根据一个方面，用户将特殊的日志命令插入到可编程图形硬件执行的指令中的软件程序中。根据流控制协议，硬件在运行时将数据写入外部存储器，软件驱动程序从存储器中读取数据以显示给用户。

6. 发明授权

US10241799B2 Out-of-order command execution with sliding windows to maintain completion statuses 有权
公开(公告)号：US10241799B2
公开(公告)日：2019-03-26
申请号：US12837600
申请日：2010-07-16
申请人： Alexei V. Bourd , Guofang Jiao
发明人： Alexei V. Bourd , Guofang Jiao
IPC分类号： G06F9/30 , G06F9/38 , G06T1/20
摘要： Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.

7. 发明授权

US08269775B2 Discarding of vertex points during two-dimensional graphics rendering using three-dimensional graphics hardware 有权
标题翻译：使用三维图形硬件在二维图形渲染期间舍弃顶点
公开(公告)号：US08269775B2
公开(公告)日：2012-09-18
申请号：US12331273
申请日：2008-12-09
申请人： Alexei V. Bourd , Guofang Jiao , Jay C. Yun
发明人： Alexei V. Bourd , Guofang Jiao , Jay C. Yun
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： This disclosure describes techniques for removing vertex points during two-dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.
摘要翻译：本公开描述了使用三维（3D）图形硬件在二维（2D）图形渲染期间去除顶点的技术。根据描述的技术，可以使用3D图形硬件在2D图形渲染期间移除一个或多个顶点。例如，这些技术可以通过丢弃在显示坐标空间中具有与先前顶点相同的位置坐标的顶点来去除显示坐标空间中的冗余顶点。或者或另外，这些技术可以去除位于直线上的多余顶点。去除位于直线上的冗余顶点或顶点可以更有效地利用GPU的硬件资源，并提高GPU渲染图像以进行显示的速度。

8. 发明申请

US20120017069A1 OUT-OF-ORDER COMMAND EXECUTION 审中-公开
标题翻译：不合格的命令执行
公开(公告)号：US20120017069A1
公开(公告)日：2012-01-19
申请号：US12837600
申请日：2010-07-16
申请人： Alexei V. Bourd , Guofang Jiao
发明人： Alexei V. Bourd , Guofang Jiao
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/3885 , G06T1/20
摘要： Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.
摘要翻译：描述了用于重新排序命令以提高至少一个命令流可以执行的速度的技术。在将至少一个命令流中的命令分配到多个管线之前，多媒体处理器分析任何流水线间依赖性并确定管道的当前执行状态。基于该信息，处理器可以通过对缺少任何当前依赖性的命令进行优先级排序来重新排序至少一个命令流，因此可以由适当的管道立即执行。在至少一个命令流中命令执行的这种不正常执行可以通过增加命令流被执行的速率来增加多媒体处理器的吞吐量。

9. 发明申请

US20090027407A1 DATA ACCESS TOOL FOR PROGRAMMABLE GRAPHICS HARDWARE 有权
标题翻译：数据访问工具可编程图形硬件
公开(公告)号：US20090027407A1
公开(公告)日：2009-01-29
申请号：US11782509
申请日：2007-07-24
申请人： Alexei V. Bourd , Guofang Jiao , Lin Chen
发明人： Alexei V. Bourd , Guofang Jiao , Lin Chen
IPC分类号： G06T1/00
CPC分类号： G06T15/005
摘要： Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user.
摘要翻译：提供了在可编程图形硬件内访问数据的方法和装置。根据一个方面，用户将特殊的日志命令插入到可编程图形硬件执行的指令中的软件程序中。根据流控制协议，硬件在运行时将数据写入外部存储器，软件驱动程序从存储器读取数据以显示给用户。

10. 发明申请

US20080111825A1 PIXEL CACHE FOR 3D GRAPHICS CIRCUITRY 有权
标题翻译：用于3D图形电路的PIXEL CACHE
公开(公告)号：US20080111825A1
公开(公告)日：2008-05-15
申请号：US11621052
申请日：2007-01-08
申请人： William Torzewski , Chun Yu , Alexei V. Bourd
发明人： William Torzewski , Chun Yu , Alexei V. Bourd
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06F12/0875 , G06F12/127
摘要： Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.
摘要翻译：提供了包括设备存储器，硬件实体，子图像单元值高速缓存和高速缓存写入操作符的装置。至少一些硬件实体执行涉及对设备存储器的访问和使用的动作。硬件实体包括用于处理来自原始对象的3D图像的3D图形电路，用于准备显示。高速缓存与设备存储器分离，并被提供以保存数据，包括缓冲的子图像单元值。高速缓存连接到3D图形电路，使得3D图形电路的像素处理部分访问高速缓存中缓冲的子图像单元值，代替直接访问设备存储器中的子图像单元值的像素处理部分。写操作符将缓冲的子图像单元格值在优先级方案的方向下写入设备存储器。优先级方案保留在与一个或多个原始对象相邻的缓存边界单元格值中。

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