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1. 发明授权

US08760457B2 Data access tool for programmable graphics hardware 有权
标题翻译：可编程图形硬件的数据访问工具
公开(公告)号：US08760457B2
公开(公告)日：2014-06-24
申请号：US11782509
申请日：2007-07-24
申请人： Alexei V. Bourd , Guofang Jiao , Lin Chen
发明人： Alexei V. Bourd , Guofang Jiao , Lin Chen
IPC分类号： G09G5/39 , G06T1/00 , G06T15/00 , G06F15/16
CPC分类号： G06T15/005
摘要： Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user.
摘要翻译：提供了在可编程图形硬件内访问数据的方法和装置。根据一个方面，用户将特殊的日志命令插入到可编程图形硬件执行的指令中的软件程序中。根据流控制协议，硬件在运行时将数据写入外部存储器，软件驱动程序从存储器中读取数据以显示给用户。

2. 发明申请

US20130227521A1 VALIDATION OF APPLICATIONS FOR GRAPHICS PROCESSING UNIT 有权
公开(公告)号：US20130227521A1
公开(公告)日：2013-08-29
申请号：US13406272
申请日：2012-02-27
申请人： Alexei V. Bourd , Jay Chunsup Yun
发明人： Alexei V. Bourd , Jay Chunsup Yun
IPC分类号： G06F9/44 , G06F9/45 , G06F21/00
CPC分类号： G06F11/3604 , G06F8/30 , G06F11/0736 , G06F11/0751 , G06F11/0793 , G06F11/3612 , G06F11/3652 , G06F11/3664 , G06F21/566 , G06F2221/033
摘要： The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.

3. 发明授权

US08884972B2 Graphics processor with arithmetic and elementary function units 有权
标题翻译：具有算术和基本功能单元的图形处理器
公开(公告)号：US08884972B2
公开(公告)日：2014-11-11
申请号：US11441696
申请日：2006-05-25
申请人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
发明人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
IPC分类号： G06F15/16 , G06F15/00 , G06T1/00 , G06F9/38 , G06F9/30
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

4. 发明申请

US20120069035A1 INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM 有权
标题翻译：多处理器计算平台中的处理器间通信技术
公开(公告)号：US20120069035A1
公开(公告)日：2012-03-22
申请号：US13235266
申请日：2011-09-16
申请人： Alexei V. Bourd , Colin Christopher Sharp , David Rigel Garcia Garcia , Chihong Zhang
发明人： Alexei V. Bourd , Colin Christopher Sharp , David Rigel Garcia Garcia , Chihong Zhang
IPC分类号： G06F15/167
CPC分类号： G06F9/544 , G06F9/54 , G06F9/546 , G06T1/20 , G06T1/60
摘要： This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.
摘要翻译：本公开描述了可以在多处理器计算平台内使用的通信技术。在一些示例中，这些技术可以提供软件接口，其可以用于支持使用命令队列发起任务的多处理器计算平台内的消息传递。在另外的示例中，这些技术可以提供可用于多处理器计算平台内的共享存储器处理器间通信的软件接口。在另外的示例中，这些技术可以提供图形处理单元（GPU），其包括用于支持GPU和主机CPU之间的消息传递和/或共享存储器通信的硬件。

5. 发明申请

US20080111825A1 PIXEL CACHE FOR 3D GRAPHICS CIRCUITRY 有权
标题翻译：用于3D图形电路的PIXEL CACHE
公开(公告)号：US20080111825A1
公开(公告)日：2008-05-15
申请号：US11621052
申请日：2007-01-08
申请人： William Torzewski , Chun Yu , Alexei V. Bourd
发明人： William Torzewski , Chun Yu , Alexei V. Bourd
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06F12/0875 , G06F12/127
摘要： Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.
摘要翻译：提供了包括设备存储器，硬件实体，子图像单元值高速缓存和高速缓存写入操作符的装置。至少一些硬件实体执行涉及对设备存储器的访问和使用的动作。硬件实体包括用于处理来自原始对象的3D图像的3D图形电路，用于准备显示。高速缓存与设备存储器分离，并被提供以保存数据，包括缓冲的子图像单元值。高速缓存连接到3D图形电路，使得3D图形电路的像素处理部分访问高速缓存中缓冲的子图像单元值，代替直接访问设备存储器中的子图像单元值的像素处理部分。写操作符将缓冲的子图像单元格值在优先级方案的方向下写入设备存储器。优先级方案保留在与一个或多个原始对象相邻的缓存边界单元格值中。

6. 发明申请

US20070273698A1 Graphics processor with arithmetic and elementary function units 有权
标题翻译：具有算术和基本功能单元的图形处理器
公开(公告)号：US20070273698A1
公开(公告)日：2007-11-29
申请号：US11441696
申请日：2006-05-25
申请人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
发明人： Yun Du , Guofang Jiao , Chun Yu , Alexei V. Bourd
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

7. 发明授权

US10241799B2 Out-of-order command execution with sliding windows to maintain completion statuses 有权
公开(公告)号：US10241799B2
公开(公告)日：2019-03-26
申请号：US12837600
申请日：2010-07-16
申请人： Alexei V. Bourd , Guofang Jiao
发明人： Alexei V. Bourd , Guofang Jiao
IPC分类号： G06F9/30 , G06F9/38 , G06T1/20
摘要： Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.

8. 发明授权

US09645866B2 Inter-processor communication techniques in a multiple-processor computing platform 有权
公开(公告)号：US09645866B2
公开(公告)日：2017-05-09
申请号：US13235236
申请日：2011-09-16
申请人： Alexei V. Bourd , Colin Christopher Sharp , David Rigel Garcia Garcia , Chihong Zhang
发明人： Alexei V. Bourd , Colin Christopher Sharp , David Rigel Garcia Garcia , Chihong Zhang
IPC分类号： G06F9/54 , G06T1/20 , G06T1/60
CPC分类号： G06F9/544 , G06F9/54 , G06F9/546 , G06T1/20 , G06T1/60
摘要： This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

9. 发明授权

US09019289B2 Execution of graphics and non-graphics applications on a graphics processing unit 有权
标题翻译：在图形处理单元上执行图形和非图形应用程序
公开(公告)号：US09019289B2
公开(公告)日：2015-04-28
申请号：US13414450
申请日：2012-03-07
申请人： Alexei V. Bourd
发明人： Alexei V. Bourd
IPC分类号： G06T1/20 , G06F9/50
CPC分类号： G06T1/20 , G06F9/5044 , G06F9/5094 , Y02D10/22
摘要： The techniques described in this disclosure are directed to efficient parallel execution of graphics and non-graphics application on a graphics processing unit (GPU). The GPU may include a plurality of shader cores within a shader processor. The techniques may reserve one or more shader cores to execute the graphics application and reserve one or more other shader cores to execute the non-graphics application. In this manner, the execution of the non-graphics application may not interfere with the execution of the graphics application, and vice-versa.
摘要翻译：本公开中描述的技术涉及图形处理单元（GPU）上的图形和非图形应用的高效并行执行。 GPU可以在着色器处理器内包括多个着色器核心。这些技术可以预留一个或多个着色器核来执行图形应用并且保留一个或多个其他着色器核来执行非图形应用。以这种方式，非图形应用的执行可能不干扰图形应用的执行，反之亦然。

10. 发明申请

US20120069029A1 INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM 有权
公开(公告)号：US20120069029A1
公开(公告)日：2012-03-22
申请号：US13235236
申请日：2011-09-16
申请人： Alexei V. Bourd , Colin Christopher Sharp , David Rigel Garcia Garcia , Chihong Zhang
发明人： Alexei V. Bourd , Colin Christopher Sharp , David Rigel Garcia Garcia , Chihong Zhang
IPC分类号： G06F15/16
CPC分类号： G06F9/544 , G06F9/54 , G06F9/546 , G06T1/20 , G06T1/60
摘要： This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

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