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1. 发明授权

US08869147B2 Multi-threaded processor with deferred thread output control 有权
标题翻译：具有延迟线程输出控制的多线程处理器
公开(公告)号：US08869147B2
公开(公告)日：2014-10-21
申请号：US11445100
申请日：2006-05-31
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46 , G06F9/48 , G06F9/30 , G06F9/38
CPC分类号： G06F9/4881 , G06F9/30123 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , Y02D10/24
摘要： A multi-threaded processor is provided that internally reorders output threads thereby avoiding the need for an external output reorder buffer. The multi-threaded processor writes its thread results back to an internal memory buffer to guarantee that thread results are outputted in the same order in which the threads are received. A thread scheduler within the multi-threaded processor manages thread ordering control to avoid the need for an external reorder buffer. A compiler for the multi-threaded processor converts instructions that would normally send processed results directly to an external reorder buffer so that the processed thread results are instead sent to the internal memory buffer of the multi-threaded processor.
摘要翻译：提供一种多线程处理器，其内部重新排序输出线程，从而避免需要外部输出重排序缓冲器。多线程处理器将其线程结果写回内部存储器缓冲区，以保证以与接收线程相同的顺序输出线程结果。多线程处理器内的线程调度器管理线程排序控制，以避免需要外部重排序缓冲区。用于多线程处理器的编译器将通常将处理结果直接发送到外部重排序缓冲器的指令转换成经处理的线程结果而不是发送到多线程处理器的内部存储器缓冲区。

2. 发明授权

US08766996B2 Unified virtual addressed register file 有权
标题翻译：统一的虚拟寻址寄存器文件
公开(公告)号：US08766996B2
公开(公告)日：2014-07-01
申请号：US11472701
申请日：2006-06-21
申请人： Yun Du , Guofang Jiao , Chun Yu , De Dzwo Hsu
发明人： Yun Du , Guofang Jiao , Chun Yu , De Dzwo Hsu
IPC分类号： G09G5/36
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/30138 , G06F9/384 , G06T15/005
摘要： A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.
摘要翻译：提供了多线程处理器，例如着色器处理器，具有由多个线程共享的内部统一存储器空间，并且根据需要动态分配给线程。映射表将虚拟寄存器映射到统一存储空间中的可用内部地址，以便线程寄存器可以存储在连续或不连续的存储器地址中。虚拟寄存器的动态大小允许根据线程寄存器中数据的类型和大小灵活分配统一存储空间。另一个特征提供了用于将统计存储器空间中的图形数据存储以改善从存储器空间获取和存储操作的有效方法。特别地，线程中的四个像素的像素数据被存储在具有独立输入/输出端口的四个存储器件中，这些存储器件允许以单个时钟周期读取四个像素进行处理。

3. 发明授权

US08345053B2 Graphics processors with parallel scheduling and execution of threads 有权
标题翻译：具有并行调度和线程执行的图形处理器
公开(公告)号：US08345053B2
公开(公告)日：2013-01-01
申请号：US11533880
申请日：2006-09-21
申请人： Guofang Jiao , Yun Du , Chun Yu
发明人： Guofang Jiao , Yun Du , Chun Yu
IPC分类号： G06F15/80 , G06F15/00 , G06T1/00
CPC分类号： G06T15/005
摘要： A graphics processor capable of parallel scheduling and execution of multiple threads, and techniques for achieving parallel scheduling and execution, are described. The graphics processor may include multiple hardware units and a scheduler. The hardware units are operable in parallel, with each hardware unit supporting a respective set of operations. The hardware units may include an ALU core, an elementary function core, a logic core, a texture sampler, a load control unit, some other hardware unit, or a combination thereof. The scheduler dispatches instructions for multiple threads to the hardware units concurrently. The graphics processor may further include an instruction cache to store instructions for threads and register banks to store data. The instruction cache and register banks may be shared by the hardware units.
摘要翻译：描述了能够并行调度和执行多个线程的图形处理器以及用于实现并行调度和执行的技术。图形处理器可以包括多个硬件单元和调度器。硬件单元可并行操作，每个硬件单元支持相应的一组操作。硬件单元可以包括ALU核，基本功能核心，逻辑核心，纹理采样器，负载控制单元，一些其他硬件单元或其组合。调度器将多个线程的指令同时分配到硬件单元。图形处理器还可以包括指令高速缓存以存储线程和寄存器组以存储数据的指令。指令高速缓存和寄存器组可以由硬件单元共享。

4. 发明授权

US07685409B2 On-demand multi-thread multimedia processor 有权
标题翻译：按需多线程多媒体处理器
公开(公告)号：US07685409B2
公开(公告)日：2010-03-23
申请号：US11677362
申请日：2007-02-21
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/00
CPC分类号： G06F12/0842 , G06F9/30145 , G06F9/30167 , G06F9/382 , G06F9/383 , G06F9/3851 , G06F9/3885 , G06F9/45558 , G06F9/5016 , G06F12/10 , G06F2009/45579 , G06F2009/45583 , Y02D10/13 , Y02D10/22
摘要： A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, data, and state information for the applications and assignable processing units to perform various types of processing for the applications. The configurable storage resources may include an instruction cache to store instructions for the applications, register banks to store data for the applications, context registers to store state information for threads of the applications, etc. The processing units may include an arithmetic logic unit (ALU) core, an elementary function core, a logic core, a texture sampler, a load control unit, a flow controller, etc. The multimedia processor allocates a configurable portion of the storage resources to each application and dynamically assigns the processing units to the applications as requested by these applications.
摘要翻译：一种设备包括多媒体处理器，其可以同时支持用于各种类型的多媒体（例如图形，音频，视频，照相机，游戏等）的多个应用。多媒体处理器包括可配置的存储资源以存储用于应用的指令，数据和状态信息以及可分配处理单元来执行用于应用的各种类型的处理。可配置的存储资源可以包括用于存储用于应用的指令的指令高速缓存，寄存器组存储用于应用的数据，上下文寄存器以存储用于应用的线程的状态信息等。处理单元可以包括算术逻辑单元（ALU ）核心，基本功能核心，逻辑核心，纹理采样器，负载控制单元，流量控制器等。多媒体处理器将存储资源的可配置部分分配给每个应用，并且将处理单元动态地分配给应用按照这些应用的要求。

5. 发明申请

US20090073168A1 FRAGMENT SHADER BYPASS IN A GRAPHICS PROCESSING UNIT, AND APPARATUS AND METHOD THEREOF 有权
标题翻译：图形处理单元中的片状阴影旁边，及其装置及方法
公开(公告)号：US20090073168A1
公开(公告)日：2009-03-19
申请号：US11855832
申请日：2007-09-14
申请人： Guofang Jiao , Yun Du , Chun Yu
发明人： Guofang Jiao , Yun Du , Chun Yu
IPC分类号： G06T15/50
CPC分类号： G06T15/005
摘要： Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to “turn off” power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.
摘要翻译：配置信息用于确定通过图形处理单元的着色器单元绕过片段着色，着色器单元能够执行顶点着色和片段着色。基于确定，着色器单元执行顶点着色并绕过片段着色。可以使用除着色器单元之外的处理元件，例如像素混合器，以执行某些片段着色。在绕过片段着色的情况下，Power被设计为“关闭”未使用组件的电源。例如，功率可以关闭到多个算术逻辑单元，着色器单元使用减少数量的算术逻辑单元来执行顶点着色。着色器单元的至少一个寄存器组可以用作FIFO缓冲器，其存储与纹理数据一起使用的像素属性数据，以分割另一个处理元件的着色操作。

6. 发明申请

US20080094412A1 3-D CLIPPING IN A GRAPHICS PROCESSING UNIT 有权
标题翻译：图形处理单元中的3-D剪辑
公开(公告)号：US20080094412A1
公开(公告)日：2008-04-24
申请号：US11551900
申请日：2006-10-23
申请人： Guofang Jiao , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G09G5/00
CPC分类号： G06T1/20 , G06T11/40 , G06T11/60 , G06T15/005 , G06T15/30 , G06T19/00 , G09G5/393
摘要： A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.
摘要翻译：图形处理单元（GPU）使用用于其他图形功能的处理单元有效地执行三维（3-D）剪辑。 GPU包括第一和第二硬件单元和至少一个缓冲器。第一硬件单元使用用于第一图形功能的第一处理单元（例如用于三角形设置的ALU，深度梯度设置等）来对原语执行3-D限幅。第一硬件单元可以通过（ a）计算每个图元的每个顶点的剪辑代码，（b）基于所述基元的所有顶点的剪辑代码来确定是否传递，丢弃或剪切每个图元，以及（c）剪切要针对剪切平面剪切的每个图元。第二硬件单元计算由3-D限幅产生的新顶点的属性分量值，例如使用用于属性梯度设置，属性插值等的ALU。该缓冲器存储3-D限幅的中间结果。

7. 发明申请

US20080059966A1 DEPENDENT INSTRUCTION THREAD SCHEDULING 有权
标题翻译：相关指令线程调度
公开(公告)号：US20080059966A1
公开(公告)日：2008-03-06
申请号：US11468221
申请日：2006-08-29
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3838
摘要： A thread scheduler includes context units for managing the execution of threads where each context unit includes a load reference counter for maintaining a counter value indicative of a difference between a number of data requests and a number of data returns associated with the particular context unit. A context controller of the thread context unit is configured to refrain from forwarding an instruction of a thread when the counter value is nonzero and the instruction includes a data dependency indicator indicating the instruction requires data returned by a previous instruction.
摘要翻译：线程调度器包括用于管理线程执行的上下文单元，其中每个上下文单元包括负载参考计数器，用于维持指示多个数据请求与与特定上下文单元相关联的数据返回数量之间的差异的计数器值。线程上下文单元的上下文控制器被配置为当计数器值非零时避免转发线程的指令，并且该指令包括指示该指令需要先前指令返回的数据的数据依赖指示符。

8. 发明申请

US20080059756A1 RELATIVE ADDRESS GENERATION 有权
标题翻译：相对地址生成
公开(公告)号：US20080059756A1
公开(公告)日：2008-03-06
申请号：US11469347
申请日：2006-08-31
申请人： Yun Du , Chun Yu , Guofang Jiao
发明人： Yun Du , Chun Yu , Guofang Jiao
IPC分类号： G06F12/10
CPC分类号： G06F12/06 , G06F9/345 , G06F9/355 , G06F9/3802 , G06F9/3875
摘要： Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address comprised of a base address and an offset, obtains a base value for the base address, sums the base value with the offset, and provides an absolute address corresponding to the relative address. The storage unit receives the base address and provides the base value to the address generator. The storage unit also receives the absolute address and provides data at this address. The address generator may derive the absolute address in a first clock cycle of a memory access. The storage unit may provide the data in a second clock cycle of the memory access. The storage unit may have multiple (e.g., two) read ports to support concurrent address generation and data retrieval.
摘要翻译：描述了有效处理相对寻址的技术。在一种设计中，处理器包括地址发生器和存储单元。地址生成器接收由基地址和偏移组成的相对地址，获得基地址的基值，将基本值与偏移量相加，并提供与相对地址对应的绝对地址。存储单元接收基地址并将其提供给地址生成器。存储单元还接收绝对地址，并在该地址处提供数据。地址生成器可以在存储器访问的第一时钟周期中导出绝对地址。存储单元可以在存储器访问的第二时钟周期中提供数据。存储单元可以具有多个（例如两个）读端口，以支持并发地址生成和数据检索。

9. 发明申请

US20080030513A1 Graphics processing unit with extended vertex cache 有权
标题翻译：具有扩展顶点缓存的图形处理单元
公开(公告)号：US20080030513A1
公开(公告)日：2008-02-07
申请号：US11499187
申请日：2006-08-03
申请人： Guofang Jiao , Brian Evan Ruttenberg , Chun Yu , Yun Du
发明人： Guofang Jiao , Brian Evan Ruttenberg , Chun Yu , Yun Du
IPC分类号： G06T1/60
CPC分类号： G06T15/005
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.
摘要翻译：描述了使用扩展顶点高速缓存处理具有图形处理单元（GPU）的计算机化图像的技术。这些技术包括创建一个连接到GPU流水线的扩展顶点缓存，以减少通过GPU流水线的数据量。 GPU流水线接收图像的图像几何，并在扩展顶点高速缓存中存储图像几何中的顶点的属性。 GPU流水线仅通过顶点坐标，其顶点和顶点高速缓存索引值指示扩展顶点高速缓存中每个顶点的属性的存储位置，沿着GPU流水线到其他处理阶段。本文描述的技术将属性梯度的设置延迟到GPU管线中的属性插值之前。可以从扩展顶点高速缓存中检索顶点属性，以便在GPU管线中的属性插值之前进行属性梯度设置。

10. 发明申请

US20080028152A1 Tiled cache for multiple software programs 有权
标题翻译：多个软件程序的平铺缓存
公开(公告)号：US20080028152A1
公开(公告)日：2008-01-31
申请号：US11493444
申请日：2006-07-25
申请人： Yun Du , Guofang Jiao , Chun Yu , De Dzwo Hsu
发明人： Yun Du , Guofang Jiao , Chun Yu , De Dzwo Hsu
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0864 , G06F9/3802 , G06F9/3851 , G06F12/0842
摘要： Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.
摘要翻译：描述用于存储用于多个软件程序的指令，常数值和其他类型的数据的缓存技术。高速缓存为多个程序提供存储，并分区成多个瓦片。每个瓦片可分配给一个程序。可以基于程序的高速缓存使用，可用的瓦片和/或其它因素来为每个程序分配任意数量的瓦片。缓存控制器识别分配给程序的块，并生成用于访问高速缓存的高速缓存地址。缓存可以被划分成物理块。高速缓存控制器可以向程序分配逻辑块，并且可以将逻辑块映射到高速缓存内的物理块。逻辑和物理瓦片的使用可以简化瓦片的分配和管理。

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