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1. 发明申请

US20100219908A1 DIGITAL TO ANALOG CONVERTING METHOD AND DIGITAL TO ANALOG CONVERTOR UTILIZING THE SAME 审中-公开
标题翻译：数字转换模拟转换方法和数字转换器使用模拟转换器
公开(公告)号：US20100219908A1
公开(公告)日：2010-09-02
申请号：US12394068
申请日：2009-02-27
申请人： Li-Chun Tu , Chia-Wei Liao , Tysh-Bin Liu
发明人： Li-Chun Tu , Chia-Wei Liao , Tysh-Bin Liu
IPC分类号： H03H7/00
CPC分类号： H03M3/396 , H03M3/502
摘要： A digital to analog converter for converting a digital input signal provided by a host to an analog output signal includes a modulator receiving the digital input signal, modulating the digital input signal, and outputting a modulated signal, and a filtering circuit receiving the modulated signal, low pass filtering the modulated signal, and outputting the analog output signal to an output node. The filtering circuit includes a first switching circuit for adjusting the bandwidth of the filtering circuit according to a bandwidth switching signal.
摘要翻译：用于将由主机提供的数字输入信号转换为模拟输出信号的数模转换器包括调制器，接收数字输入信号，调制数字输入信号并输出调制信号，以及滤波电路接收调制信号，低通滤波调制信号，并将模拟输出信号输出到输出节点。滤波电路包括：第一切换电路，用于根据带宽切换信号调整滤波电路的带宽。

2. 发明授权

US07035960B2 Method for increasing memory in a processor 有权
标题翻译：增加处理器内存的方法
公开(公告)号：US07035960B2
公开(公告)日：2006-04-25
申请号：US10605646
申请日：2003-10-15
申请人： Li-Chun Tu , Ping-Sheng Chen , Pao-Ching Tseng , Hung-Cheng Kuo
发明人： Li-Chun Tu , Ping-Sheng Chen , Pao-Ching Tseng , Hung-Cheng Kuo
IPC分类号： G06F12/00
CPC分类号： G06F12/0623
摘要： A method for increasing the internal memory in a processor. The method includes providing an extended memory in the processor, adding bits to data addresses and register addresses with an address extender, and adding bits to stack addresses with a stack pointer generator so that the processor is capable of accessing memory addresses larger than the bit width of the command set of the processor. The method also includes carrying over the bits when the stack address exceeds the limit of the conventional memory and accessing the stack data exceeding the limit of the conventional memory in the extended memory.
摘要翻译：一种用于增加处理器内部存储器的方法。该方法包括在处理器中提供扩展存储器，向位地址扩展器添加比特到数据地址和寄存器地址，以及使用堆栈指针生成器将位添加到堆栈地址，使得处理器能够访问大于位宽的存储器地址的处理器的命令集。该方法还包括当堆栈地址超过常规存储器的限制并且访问超过扩展存储器中的常规存储器的限制的堆栈数据时承载位。

3. 发明授权

US08769188B2 Nonvolatile memory controller and method for writing data to nonvolatile memory 有权
标题翻译：非易失性存储器控制器和将数据写入非易失性存储器的方法
公开(公告)号：US08769188B2
公开(公告)日：2014-07-01
申请号：US12620722
申请日：2009-11-18
申请人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
发明人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
IPC分类号： G06F11/00 , H03M13/09 , G06F3/06
CPC分类号： H03M13/09 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F12/0246 , G06F2212/7209 , H03M13/096
摘要： The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit.
摘要翻译：本发明提供一种非易失性存储器控制器。在一个实施例中，非易失性存储器控制器接收用于从主机写入非易失性存储器的新数据，并且包括签名计算电路，签名缓冲器，签名比较电路，数据比较电路和非易失性存储器接口电路。签名计算电路根据新数据计算第一签名。签名缓冲器输出对应于存储在非易失性存储器中的旧数据的第二签名，其中旧数据具有与新数据相同的逻辑地址。签名比较电路确定第一签名是否与第二签名相同。当通过签名比较电路确定第一签名与第二签名不同时，非易失性存储器接口电路将新数据写入非易失性存储器。

4. 发明授权

US08418021B2 Storage controller with encoding/decoding circuit programmable to support different ECC requirements and related method thereof 有权
标题翻译：具有编码/解码电路的存储控制器可编程，以支持不同的ECC要求及其相关方法
公开(公告)号：US08418021B2
公开(公告)日：2013-04-09
申请号：US12645490
申请日：2009-12-23
申请人： Li-Lien Lin , Chao-Yi Wu , Chien-Chung Wu , Li-Chun Tu
发明人： Li-Lien Lin , Chao-Yi Wu , Chien-Chung Wu , Li-Chun Tu
IPC分类号： G06F11/00
CPC分类号： H03M13/152 , G06F11/1068 , H03M13/6516
摘要： One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.
摘要翻译：用于控制存储设备的数据访问的一个示例性存储控制器包括编码电路和控制电路。编码电路是可编程的，以支持多个不同的有限域，并且被实现用于根据可调节的有限域设置产生编码数据。实施控制电路，用于控制编码电路的可调节有限域设置，并根据编码数据将数据记录到存储设备中。用于控制存储设备的数据访问的另一示例性存储控制器包括解码电路和控制电路。解码电路是可编程的以支持多个不同的有限域，并且被实现用于根据可调整的有限域设置产生解码数据。控制电路实现用于从存储装置读取数据以获得读出数据并控制解码电路的可调节有限域设置。

5. 发明申请

US20070150648A1 METHOD FOR USING SERIAL FLASH MEMORY AS PROGRAM STORAGE MEDIA FOR MICROPROCESSOR AND RELATED PROCESSING SYSTEM THEREOF 审中-公开
标题翻译：使用串行闪速存储器作为微处理器的程序存储介质的方法及其相关处理系统
公开(公告)号：US20070150648A1
公开(公告)日：2007-06-28
申请号：US11673598
申请日：2007-02-12
申请人： Li-Chun Tu , Hung-Cheng Kuo , Ping-Sheng Chen
发明人： Li-Chun Tu , Hung-Cheng Kuo , Ping-Sheng Chen
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3814
摘要： A method for dynamically adjusting an operating speed of a microprocessor for the microprocessor to access at least a serial flash memory (together with a random access memory). The method includes reducing an executing speed of the microprocessor if the required data in the serial flash memory (or the random access memory) is not well prepared and executing the microprocessor at a normal speed if the required data in the serial flash memory (or the random access memory) is well prepared.
摘要翻译：一种用于动态调整微处理器的操作速度以便微处理器访问至少串行闪存（与随机存取存储器）一起的方法。如果串行闪存（或随机存取存储器）中所需的数据没有准备好并以正常速度执行微处理器（如果串行闪存中的所需数据（或随机存取存储器）做好准备。

6. 发明授权

US08971378B2 Wireless communication device 有权
标题翻译：无线通信设备
公开(公告)号：US08971378B2
公开(公告)日：2015-03-03
申请号：US13308559
申请日：2011-12-01
申请人： Li-Chun Tu , Chia-Hao Yang , Tsung-Huang Chen
发明人： Li-Chun Tu , Chia-Hao Yang , Tsung-Huang Chen
IPC分类号： H04B1/00 , H04B1/40
CPC分类号： H04B1/40
摘要： A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.
摘要翻译：提供一种包括集成处理电路和第一存储器的无线通信装置。集成处理电路包括能够处理无线通信信号的处理单元和能够执行射频（RF）信号和基带信号之间的转换的射频（RF）单元，其中无线通信信号是 RF信号和基带信号。第一存储器耦合到集成处理电路。第一存储器能够存储由处理单元使用的数据，其中集成处理电路和第一存储器封装在单个半导体封装中。

7. 发明授权

US08447917B2 Flash memory devices and methods for controlling a flash memory device 有权
标题翻译：闪存设备和用于控制闪存设备的方法
公开(公告)号：US08447917B2
公开(公告)日：2013-05-21
申请号：US12721724
申请日：2010-03-11
申请人： Yeow-Chyi Chen , Hong-Ching Chen , Li-Chun Tu , Tzu-Chieh Lin , Chi-Wei Peng
发明人： Yeow-Chyi Chen , Hong-Ching Chen , Li-Chun Tu , Tzu-Chieh Lin , Chi-Wei Peng
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.
摘要翻译：闪存器件包括存储器阵列和存储器控制电路。存储器阵列包括存储器模块。每个存储器模块位于存储器通道中并且包括预定数量的存储器单元。存储器控制电路通过地址锁存使能（ALE）引脚和命令锁存使能（CLE）引脚耦合到存储器阵列。 ALE引脚和CLE引脚耦合到所有存储单元，并由存储器阵列中的所有存储单元共享。

8. 发明申请

US20110119429A1 NONVOLATILE MEMORY CONTROLLER AND METHOD FOR WRITING DATA TO NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器控制器和将数据写入非易失性存储器的方法
公开(公告)号：US20110119429A1
公开(公告)日：2011-05-19
申请号：US12620722
申请日：2009-11-18
申请人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
发明人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： H03M13/09 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F12/0246 , G06F2212/7209 , H03M13/096
摘要： The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit.
摘要翻译：本发明提供一种非易失性存储器控制器。在一个实施例中，非易失性存储器控制器接收用于从主机写入非易失性存储器的新数据，并且包括签名计算电路，签名缓冲器，签名比较电路，数据比较电路和非易失性存储器接口电路。签名计算电路根据新数据计算第一签名。签名缓冲器输出对应于存储在非易失性存储器中的旧数据的第二签名，其中旧数据具有与新数据相同的逻辑地址。签名比较电路确定第一签名是否与第二签名相同。当通过签名比较电路确定第一签名与第二签名不同时，非易失性存储器接口电路将新数据写入非易失性存储器。

9. 发明申请

US20100251068A1 STORAGE CONTROLLER WITH ENCODING/DECODING CIRCUIT PROGRAMMABLE TO SUPPORT DIFFERENT ECC REQUIREMENTS AND RELATED METHOD THEREOF 有权
标题翻译：具有编码/解码电路的存储控制器可编程以支持不同的ECC要求及其相关方法
公开(公告)号：US20100251068A1
公开(公告)日：2010-09-30
申请号：US12645490
申请日：2009-12-23
申请人： Li-Lien Lin , Chao-Yi Wu , Chien-Chung Wu , Li-Chun Tu
发明人： Li-Lien Lin , Chao-Yi Wu , Chien-Chung Wu , Li-Chun Tu
IPC分类号： H03M13/05 , G06F11/10 , H03M13/29
CPC分类号： H03M13/152 , G06F11/1068 , H03M13/6516
摘要： One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.
摘要翻译：用于控制存储设备的数据访问的一个示例性存储控制器包括编码电路和控制电路。编码电路是可编程的，以支持多个不同的有限域，并且被实现用于根据可调节的有限域设置产生编码数据。实施控制电路，用于控制编码电路的可调节有限域设置，并根据编码数据将数据记录到存储设备中。用于控制存储设备的数据访问的另一示例性存储控制器包括解码电路和控制电路。解码电路是可编程的以支持多个不同的有限域，并且被实现用于根据可调整的有限域设置产生解码数据。控制电路实现用于从存储装置读取数据以获得读出数据并控制解码电路的可调节有限域设置。

10. 发明授权

US07111107B2 Microcontroller with dedicated memory bank for servicing interrupts 有权
标题翻译：具有专用存储体的微控制器用于维修中断
公开(公告)号：US07111107B2
公开(公告)日：2006-09-19
申请号：US10707107
申请日：2003-11-20
申请人： Pao-Ching Tseng , Ping-Cheng Sung , Ping-Sheng Chen , Li-Chun Tu
发明人： Pao-Ching Tseng , Ping-Cheng Sung , Ping-Sheng Chen , Li-Chun Tu
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F12/0623
摘要： A microcontroller with expandable memory banks has a microprocessor, a plurality of memory banks with only one page for storing interrupt service routines(ISR), a memory bank control circuit connected to the microprocessor, and a multiplexer for connecting the microprocessor with the plurality of memory banks. The memory bank control circuit generates a selection signal according to an interrupt signal and a microprocessor interrupt service routine execution end signal. The multiplexer outputs a page selection signal from the microprocessor or outputs a predetermined page selection signal according to the output signal from the memory bank control circuit.
摘要翻译：具有可扩展存储体的微控制器具有微处理器，多个存储体仅具有一页用于存储中断服务程序（ISR），连接到微处理器的存储器组控制电路以及用于将微处理器与多个存储器连接的多路复用器银行。存储体控制电路根据中断信号和微处理器中断服务程序执行结束信号产生选择信号。复用器从微处理器输出页选择信号，或者根据来自存储体控制电路的输出信号输出预定页选择信号。

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