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1. 发明授权

US07035960B2 Method for increasing memory in a processor 有权
标题翻译：增加处理器内存的方法
公开(公告)号：US07035960B2
公开(公告)日：2006-04-25
申请号：US10605646
申请日：2003-10-15
申请人： Li-Chun Tu , Ping-Sheng Chen , Pao-Ching Tseng , Hung-Cheng Kuo
发明人： Li-Chun Tu , Ping-Sheng Chen , Pao-Ching Tseng , Hung-Cheng Kuo
IPC分类号： G06F12/00
CPC分类号： G06F12/0623
摘要： A method for increasing the internal memory in a processor. The method includes providing an extended memory in the processor, adding bits to data addresses and register addresses with an address extender, and adding bits to stack addresses with a stack pointer generator so that the processor is capable of accessing memory addresses larger than the bit width of the command set of the processor. The method also includes carrying over the bits when the stack address exceeds the limit of the conventional memory and accessing the stack data exceeding the limit of the conventional memory in the extended memory.
摘要翻译：一种用于增加处理器内部存储器的方法。该方法包括在处理器中提供扩展存储器，向位地址扩展器添加比特到数据地址和寄存器地址，以及使用堆栈指针生成器将位添加到堆栈地址，使得处理器能够访问大于位宽的存储器地址的处理器的命令集。该方法还包括当堆栈地址超过常规存储器的限制并且访问超过扩展存储器中的常规存储器的限制的堆栈数据时承载位。

2. 发明申请

US20070150648A1 METHOD FOR USING SERIAL FLASH MEMORY AS PROGRAM STORAGE MEDIA FOR MICROPROCESSOR AND RELATED PROCESSING SYSTEM THEREOF 审中-公开
标题翻译：使用串行闪速存储器作为微处理器的程序存储介质的方法及其相关处理系统
公开(公告)号：US20070150648A1
公开(公告)日：2007-06-28
申请号：US11673598
申请日：2007-02-12
申请人： Li-Chun Tu , Hung-Cheng Kuo , Ping-Sheng Chen
发明人： Li-Chun Tu , Hung-Cheng Kuo , Ping-Sheng Chen
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3814
摘要： A method for dynamically adjusting an operating speed of a microprocessor for the microprocessor to access at least a serial flash memory (together with a random access memory). The method includes reducing an executing speed of the microprocessor if the required data in the serial flash memory (or the random access memory) is not well prepared and executing the microprocessor at a normal speed if the required data in the serial flash memory (or the random access memory) is well prepared.
摘要翻译：一种用于动态调整微处理器的操作速度以便微处理器访问至少串行闪存（与随机存取存储器）一起的方法。如果串行闪存（或随机存取存储器）中所需的数据没有准备好并以正常速度执行微处理器（如果串行闪存中的所需数据（或随机存取存储器）做好准备。

3. 发明授权

US07325231B2 Method and related device for updating firmware code stored in non-volatile memory 有权
标题翻译：用于更新存储在非易失性存储器中的固件代码的方法和相关设备
公开(公告)号：US07325231B2
公开(公告)日：2008-01-29
申请号：US10906298
申请日：2005-02-14
申请人： Li-Chun Tu , Ping-Sheng Chen , Yi-Chuan Chen , Sung-Yang Wu
发明人： Li-Chun Tu , Ping-Sheng Chen , Yi-Chuan Chen , Sung-Yang Wu
IPC分类号： G06F13/12
CPC分类号： G06F8/65
摘要： A non-volatile memory is installed in an electronic device. A method for updating a firmware code stored in a non-volatile memory includes: providing an updating control unit having a command set; providing the updating control unit with a trigger signal to enable at least one command of the command set; and utilizing the updating control unit to read/write the non-volatile memory according to the enabled command to update the firmware code. Wherein each command of the command set is a memory read/write command. The method further includes updating at least one command of the command set in real time. The present invention further provides an electronic device corresponding to the method.
摘要翻译：非易失性存储器安装在电子设备中。用于更新存储在非易失性存储器中的固件代码的方法包括：提供具有命令集的更新控制单元; 向所述更新控制单元提供触发信号以启用所述命令集的至少一个命令; 以及利用所述更新控制单元根据所述使能命令读/写所述非易失性存储器来更新所述固件代码。其中命令集的每个命令都是一个内存读/写命令。该方法还包括实时更新命令集的至少一个命令。本发明还提供了一种对应于该方法的电子设备。

4. 发明授权

US07607001B2 Memory management method for simultaneously loading and executing program codes 有权
标题翻译：用于同时加载和执行程序代码的内存管理方法
公开(公告)号：US07607001B2
公开(公告)日：2009-10-20
申请号：US10905304
申请日：2004-12-27
申请人： Li-Chun Tu , Ping-Sheng Chen
发明人： Li-Chun Tu , Ping-Sheng Chen
IPC分类号： G06F9/00
CPC分类号： G06F9/44521 , G06F9/4403
摘要： A method is provided for simultaneously loading and executing program code in a circuit system. The circuit system includes a plurality of memory devices, a microprocessor, and a loading circuit. The method includes dividing the program code into a plurality of code divisions and utilizing the microprocessor to execute at least a code division when the loading circuit loads any other code division into a memory device of the plurality of memory devices.
摘要翻译：提供一种用于在电路系统中同时加载和执行程序代码的方法。电路系统包括多个存储器件，微处理器和加载电路。该方法包括将程序代码分成多个代码部分，并且当加载电路将任何其他代码分段加载到多个存储器件的存储器件中时，利用微处理器执行至少一个代码划分。

5. 发明申请

US20050229172A1 METHOD AND RELATED DEVICE FOR UPDATING FIRMWARE CODE STORED IN NON-VOLATILE MEMORY 有权
标题翻译：用于更新存储在非易失性存储器中的固件代码的方法和相关设备
公开(公告)号：US20050229172A1
公开(公告)日：2005-10-13
申请号：US10906298
申请日：2005-02-14
申请人： Li-Chun Tu , Ping-Sheng Chen , Yi-Chuan Chen , Sung-Yang Wu
发明人： Li-Chun Tu , Ping-Sheng Chen , Yi-Chuan Chen , Sung-Yang Wu
IPC分类号： G06F9/44 , G06F9/445 , G06F13/00
CPC分类号： G06F8/65
摘要： A non-volatile memory is installed in an electronic device. A method for updating a firmware code stored in a non-volatile memory includes: providing an updating control unit having a command set; providing the updating control unit with a trigger signal to enable at least one command of the command set; and utilizing the updating control unit to read/write the non-volatile memory according to the enabled command to update the firmware code. Wherein each command of the command set is a memory read/write command. The method further includes updating at least one command of the command set in real time. The present invention further provides an electronic device corresponding to the method.
摘要翻译：非易失性存储器安装在电子设备中。用于更新存储在非易失性存储器中的固件代码的方法包括：提供具有命令集的更新控制单元; 向所述更新控制单元提供触发信号以启用所述命令集的至少一个命令; 以及利用所述更新控制单元根据所述使能命令读/写所述非易失性存储器来更新所述固件代码。其中命令集的每个命令都是一个内存读/写命令。该方法还包括实时更新命令集的至少一个命令。本发明还提供了一种对应于该方法的电子设备。

6. 发明申请

US20050193243A1 METHOD FOR MANAGING A CIRCUIT SYSTEM DURING MODE-SWITCHING 审中-公开
标题翻译：在模式切换期间管理电路系统的方法
公开(公告)号：US20050193243A1
公开(公告)日：2005-09-01
申请号：US10906004
申请日：2005-01-30
申请人： Li-Chun Tu , Ping-Sheng Chen
发明人： Li-Chun Tu , Ping-Sheng Chen
IPC分类号： G06F1/26 , G06F1/32 , G06F9/44
CPC分类号： G06F1/3246 , G06F1/3203
摘要： A method for switching modes of a circuit system. The circuit system includes at least a first memory device, a second memory device, and a microprocessor. The method includes utilizing the second memory device to store a program code division and utilizing the microprocessor to execute the program code division stored in the second memory device so that the microprocessor and the first memory device can accurately switch modes when the circuit system proceeds with mode-switching procedures.
摘要翻译：一种用于切换电路系统的模式的方法。该电路系统至少包括第一存储器件，第二存储器件和微处理器。该方法包括利用第二存储装置来存储程序代码划分并利用微处理器来执行存储在第二存储装置中的程序代码分区，使得当电路系统进行模式时，微处理器和第一存储装置可以准确地切换模式切换程序。

7. 发明申请

US20110119429A1 NONVOLATILE MEMORY CONTROLLER AND METHOD FOR WRITING DATA TO NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器控制器和将数据写入非易失性存储器的方法
公开(公告)号：US20110119429A1
公开(公告)日：2011-05-19
申请号：US12620722
申请日：2009-11-18
申请人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
发明人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： H03M13/09 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F12/0246 , G06F2212/7209 , H03M13/096
摘要： The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit.
摘要翻译：本发明提供一种非易失性存储器控制器。在一个实施例中，非易失性存储器控制器接收用于从主机写入非易失性存储器的新数据，并且包括签名计算电路，签名缓冲器，签名比较电路，数据比较电路和非易失性存储器接口电路。签名计算电路根据新数据计算第一签名。签名缓冲器输出对应于存储在非易失性存储器中的旧数据的第二签名，其中旧数据具有与新数据相同的逻辑地址。签名比较电路确定第一签名是否与第二签名相同。当通过签名比较电路确定第一签名与第二签名不同时，非易失性存储器接口电路将新数据写入非易失性存储器。

8. 发明授权

US07111107B2 Microcontroller with dedicated memory bank for servicing interrupts 有权
标题翻译：具有专用存储体的微控制器用于维修中断
公开(公告)号：US07111107B2
公开(公告)日：2006-09-19
申请号：US10707107
申请日：2003-11-20
申请人： Pao-Ching Tseng , Ping-Cheng Sung , Ping-Sheng Chen , Li-Chun Tu
发明人： Pao-Ching Tseng , Ping-Cheng Sung , Ping-Sheng Chen , Li-Chun Tu
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F12/0623
摘要： A microcontroller with expandable memory banks has a microprocessor, a plurality of memory banks with only one page for storing interrupt service routines(ISR), a memory bank control circuit connected to the microprocessor, and a multiplexer for connecting the microprocessor with the plurality of memory banks. The memory bank control circuit generates a selection signal according to an interrupt signal and a microprocessor interrupt service routine execution end signal. The multiplexer outputs a page selection signal from the microprocessor or outputs a predetermined page selection signal according to the output signal from the memory bank control circuit.
摘要翻译：具有可扩展存储体的微控制器具有微处理器，多个存储体仅具有一页用于存储中断服务程序（ISR），连接到微处理器的存储器组控制电路以及用于将微处理器与多个存储器连接的多路复用器银行。存储体控制电路根据中断信号和微处理器中断服务程序执行结束信号产生选择信号。复用器从微处理器输出页选择信号，或者根据来自存储体控制电路的输出信号输出预定页选择信号。

9. 发明申请

US20050144364A1 MEMORY MANAGEMENT METHOD FOR SIMULTANEOUSLY LOADING AND EXECUTING PROGRAM CODES 有权
标题翻译：用于同时加载和执行程序代码的内存管理方法
公开(公告)号：US20050144364A1
公开(公告)日：2005-06-30
申请号：US10905304
申请日：2004-12-27
申请人： Li-Chun Tu , Ping-Sheng Chen
发明人： Li-Chun Tu , Ping-Sheng Chen
IPC分类号： G06F9/00 , G06F9/44 , G06F9/445 , G06F12/00
CPC分类号： G06F9/44521 , G06F9/4403
摘要： A method is provided for simultaneously loading and executing program code in a circuit system. The circuit system includes a plurality of memory devices, a microprocessor, and a loading circuit. The method includes dividing the program code into a plurality of code divisions and utilizing the microprocessor to execute at least a code division when the loading circuit loads any other code division into a memory device of the plurality of memory devices.
摘要翻译：提供一种用于在电路系统中同时加载和执行程序代码的方法。电路系统包括多个存储器件，微处理器和加载电路。该方法包括将程序代码分成多个代码部分，并且当加载电路将任何其他代码分段加载到多个存储器件的存储器件中时，利用微处理器执行至少一个代码划分。

10. 发明授权

US08769188B2 Nonvolatile memory controller and method for writing data to nonvolatile memory 有权
标题翻译：非易失性存储器控制器和将数据写入非易失性存储器的方法
公开(公告)号：US08769188B2
公开(公告)日：2014-07-01
申请号：US12620722
申请日：2009-11-18
申请人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
发明人： Li-Chun Tu , Chao-Yi Wu , Ping-Sheng Chen
IPC分类号： G06F11/00 , H03M13/09 , G06F3/06
CPC分类号： H03M13/09 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F12/0246 , G06F2212/7209 , H03M13/096
摘要： The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit.
摘要翻译：本发明提供一种非易失性存储器控制器。在一个实施例中，非易失性存储器控制器接收用于从主机写入非易失性存储器的新数据，并且包括签名计算电路，签名缓冲器，签名比较电路，数据比较电路和非易失性存储器接口电路。签名计算电路根据新数据计算第一签名。签名缓冲器输出对应于存储在非易失性存储器中的旧数据的第二签名，其中旧数据具有与新数据相同的逻辑地址。签名比较电路确定第一签名是否与第二签名相同。当通过签名比较电路确定第一签名与第二签名不同时，非易失性存储器接口电路将新数据写入非易失性存储器。

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