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1. 发明申请

US20180241409A1 CONTINUOUS-TIME DELTA-SIGMA ADC WITH SCALABLE SAMPLING RATES AND EXCESS LOOP DELAY COMPENSATION 审中-公开
公开(公告)号：US20180241409A1
公开(公告)日：2018-08-23
申请号：US15440612
申请日：2017-02-23
申请人： QUALCOMM Incorporated
发明人： Elias DAGHER , Yan WANG , Mohammad Meysam ZARGHAM , Dinesh Jagannath ALLADI
IPC分类号： H03M1/12 , H03M3/00
CPC分类号： H03M1/1245 , H03M3/37 , H03M3/396 , H03M3/458 , H03M3/464
摘要： Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

2. 发明授权

US09639203B2 Touch control detection system, delta-sigma modulator and modulating method thereof 有权
公开(公告)号：US09639203B2
公开(公告)日：2017-05-02
申请号：US14582215
申请日：2014-12-24
申请人： Novatek Microelectronics Corp.
发明人： Chih-Yuan Chang
IPC分类号： G06F3/041 , H03M3/00
CPC分类号： G06F3/0416 , H03M3/396 , H03M3/422 , H03M3/438 , H03M3/458
摘要： A touch control detection system, a delta-sigma modulator and a modulating method thereof are provided. The delta-sigma modulator includes a quantizer and N integrating units. The quantizer generates a modulating result signal. The integrating units are coupled in series. Each of the integrating receives an input signal, and each of the integrating units receives a plurality of gain parameters, N is a positive integer. The quantizer quantizes a signal on an output end of the Nth stage integrating unit according to an error signal for generating the modulating result signal. A center frequency of a noise transfer function (NTF) of the delta-sigma modulator is adjusted according to the gain parameters, and the gain parameters are determined according to a frequency of the input signal.

3. 发明授权

US08749417B2 Multi-mode analog-to-digital converter 有权
标题翻译：多模式模数转换器
公开(公告)号：US08749417B2
公开(公告)日：2014-06-10
申请号：US13344143
申请日：2012-01-05
申请人： Abdulkerim L. Coban , Clayton H. Daigle , Alessandro Piovaccari
发明人： Abdulkerim L. Coban , Clayton H. Daigle , Alessandro Piovaccari
IPC分类号： H03M3/00 , H03M1/12 , H03M7/20
CPC分类号： H03M3/394 , H03M3/396 , H03M3/398 , H03M3/40 , H03M3/448 , H03M3/45 , H03M3/452 , H03M3/454 , H04N21/6112 , H04N21/6118 , H04N21/6143
摘要： A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.
摘要翻译：配置模数转换器（ADC）的方法包括根据控制信号的值将ADC配置为以低通滤波器模式和带通滤波器模式之一工作。在至少一个实施例中，该方法还包括基于选择低中频（LIF）模式和零中频（ZIF）之一来配置ADC的积分器增益和ADC的前馈增益，模式。

4. 发明授权

US08451051B2 Dual mode sigma delta analog to digital converter and circuit using the same 有权
标题翻译：双模Σ-Δ模数转换器和电路使用相同
公开(公告)号：US08451051B2
公开(公告)日：2013-05-28
申请号：US13252981
申请日：2011-10-04
申请人： Yi-Lung Chen
发明人： Yi-Lung Chen
IPC分类号： H03K5/00 , H03M3/00
CPC分类号： H03M3/396 , H04B1/30
摘要： The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator; a second switched-capacitor integrator; a quantizer; a feedback circuit and a mode device. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF.
摘要翻译：本发明提供了一种仅在一个硬件实现中用于低IF和近零IF接收机的双模Σ-Δ模数转换器（ADC）。双模Σ-ΔADC包括第一开关电容积分器; 第二开关电容器积分器; 量化器反馈电路和模式设备。通过打开或关闭模式设备，可以轻松地改变所公开的ADC的配置，以确定接收信号落入低IF或接近零IF。

5. 发明授权

US07193544B1 Parallel, adaptive delta sigma ADC 失效
标题翻译：并行，自适应Δ西格玛ADC
公开(公告)号：US07193544B1
公开(公告)日：2007-03-20
申请号：US11220712
申请日：2005-09-08
申请人： Michael M. Fitelson , Aaron Pesetski , Alfred P. Turley
发明人： Michael M. Fitelson , Aaron Pesetski , Alfred P. Turley
IPC分类号： H03M3/00
CPC分类号： H03M3/396 , H03M3/388 , H03M3/468
摘要： An apparatus performs adaptive analog-to-digital conversion. The apparatus according to one embodiment comprises a frequency modulator unit for changing an input analog signal into a modulated analog signal with a frequency spectrum in a bandwidth of interest, a parallel delta sigma conversion unit operatively connected to the frequency modulator unit, the parallel delta sigma conversion unit converting the modulated analog signal into a digital signal, and a controller operatively connected to the frequency modulator unit and the parallel delta sigma conversion unit, the controller adjusting at least one parameter relating to a frequency characteristic of the frequency modulator unit and/or the parallel delta sigma conversion unit.
摘要翻译：一种装置执行自适应模数转换。根据一个实施例的装置包括：频率调制器单元，用于将输入的模拟信号改变成具有感兴趣带宽中的频谱的经调制的模拟信号，可操作地连接到频率调制器单元的并行ΔΣ转换单元，并行Δ西格玛转换单元将调制的模拟信号转换为数字信号，以及可操作地连接到频率调制器单元和并行ΔΣ转换单元的控制器，所述控制器调整与频率调制器单元的频率特性相关的至少一个参数和/或并行ΔΣ转换单元。

6. 发明申请

US20050237233A1 Programmbale loop filter for use with a sigma delta analog-to-digital converter and method of programming the same 有权
标题翻译：用于Σ-Δ模数转换器的编程环路滤波器及其编程方法
公开(公告)号：US20050237233A1
公开(公告)日：2005-10-27
申请号：US10832531
申请日：2004-04-27
申请人： Khurram Muhammad
发明人： Khurram Muhammad
IPC分类号： H03H7/12 , H03M3/02 , H03M3/00
CPC分类号： H03M3/396 , H03M3/392 , H03M3/43
摘要： The present invention is directed to a programmable loop filter, a method of programming the same and a sigma delta analog-to-digital converter (ADC) incorporating the programmable loop filter or the method. In one embodiment, the programmable loop filter includes: (1) a configurable filter structure containing selectably interconnectable alternative filter elements and (2) a configuration controller coupled to the configurable filter structure and operable to interconnect at least a selected one of the filter elements to determine a transfer characteristic of the configurable filter structure and set an operating condition of the sigma delta ADC.
摘要翻译：本发明涉及一种可编程环路滤波器，其编程方法以及结合有可编程环路滤波器或该方法的Σ-Δ模数转换器（ADC）。在一个实施例中，可编程环路滤波器包括：（1）包含可选择地互连的替代滤波器元件的可配置滤波器结构，以及（2）耦合到可配置滤波器结构并且可操作以将至少一个所选滤波器元件互连到确定可配置滤波器结构的传输特性并设置Σ-ΔADC的工作状态。

7. 发明申请

US20020154046A1 ULTRA-WIDE BAND (20 MHZ TO 5 GHZ) ANALOG TO DIGITAL SIGNAL PROCESSOR 有权
标题翻译：超宽带（20 MHZ至5 GHZ）模拟到数字信号处理器
公开(公告)号：US20020154046A1
公开(公告)日：2002-10-24
申请号：US09837134
申请日：2001-04-18
发明人： Cornell Drentea
IPC分类号： H03M003/00
CPC分类号： H03M3/396 , H03M3/402 , H03M3/458
摘要： An ultra-wide band general purpose analog to digital signal processor (200) covering the radio frequency range from 20 MHz to 5 GHz. The processor (200) includes a first circuit for shifting a frequency of an input signal, a second circuit for processing the input signal, and a third circuit for selectively bypassing the first circuit whereby the input signal is provided directly to the second circuit in a first mode of operation and to the second circuit via the first circuit in a second mode of operation. In the illustrative embodiment, the first circuit is a mixer (12) with a normalized mixing ratio of 0.8 to 0.9. The second circuit is a sigma-delta analog-to-digital converter (14). The third circuit is a switch (10) for passing the input signal directly to the second circuit if the input is 20 MHz to 2 GHz, or for passing the input signal to the first circuit if the input is 2 GHz to 5 GHz. In the preferred embodiment, the switch (10), the mixer (12), and the sigma-delta converter (14) are disposed on a single application specific integrated circuit (ASIC) substrate (100).
摘要翻译：一种覆盖20MHz至5GHz的射频范围的超宽带通用模数信号处理器（200）。处理器（200）包括用于移位输入信号的频率的第一电路，用于处理输入信号的第二电路，以及用于选择性地旁路第一电路的第三电路，由此输入信号直接提供给第二电路在第二操作模式下通过第一电路连接到第二电路。在说明性实施例中，第一电路是标准化混合比为0.8至0.9的混合器（12）。第二电路是Σ-Δ模数转换器（14）。如果输入为20MHz至2GHz，则第三电路是用于将输入信号直接传递到第二电路的开关（10），或者如果输入为2GHz至5GHz则将输入信号传递到第一电路。在优选实施例中，开关（10），混频器（12）和Σ-Δ转换器（14）设置在单个专用集成电路（ASIC）衬底（100）上。

8. 发明授权

US5608400A Selectable intermediate frequency sigma-delta analog-to-digital converter 失效
标题翻译：可选择的中频Σ-Δ模数转换器
公开(公告)号：US5608400A
公开(公告)日：1997-03-04
申请号：US519593
申请日：1995-08-24
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
IPC分类号： H03H17/04 , H03M3/02 , H03M3/00
CPC分类号： H03H17/04 , H03M3/404 , H03M3/396 , H03M3/438 , H03M3/456
摘要： A sigma-delta analog-to-digital converter (10) provides high loop gain for suppression of noise components by use of a regenerative feedback loop or resonator (50), which produces a comb resonance response 212), embedded in the main degenerative feedback loop (48). The main loop includes an ADC (32) which samples at a clock frequency, which in turn defines a Nyquist frequency. The main loop also includes a DAC (38) which has a transfer function (42), which is equalized by a filter (44). The resonator (50) includes a low-pass filter (52) which matches the equalized main loop transfer function, a DC block (56), and a null filter (54) which nulls the resonator gain at the comb peak which lies above the Nyquist frequency. The open-loop transfer function of the regenerative loop (50) is set to unity gain and 0.degree..+-.N 360.degree. phase at the frequency of the analog input signal. A multipole embodiment (510) has multiple regenerative loops (55o) which produce multipole noise rejection (642). Resonators (751) are used in other .SIGMA..DELTA. ADCs (790, 890).
摘要翻译： Σ-Δ模数转换器（10）通过使用嵌入在主退化反馈中的再生反馈回路或共振器（50）提供用于抑制噪声分量的高环路增益，其产生梳状共振响应212）循环（48）。主回路包括ADC（32），其以时钟频率进行采样，其又限定奈奎斯特频率。主回路还包括具有传递函数（42）的DAC（38），其由滤波器（44）均衡。谐振器（50）包括与均衡的主环路传递函数相匹配的低通滤波器（52），DC块（56）和零滤波器（54），其使位于奈奎斯特频率再生回路（50）的开环传递函数设定为模数输入信号频率下的单位增益和0°+/- N 360°相位。多极实施例（510）具有产生多极噪声抑制的多个再生回路（55o）（642）。谐振器（751）用于其他SIGMA DELTA ADC（790,890）。

9. 发明申请

US20190196652A1 SIGNAL PROCESSING CIRCUIT FOR PROCESSING SENSING SIGNAL FROM TOUCH PANEL 审中-公开
公开(公告)号：US20190196652A1
公开(公告)日：2019-06-27
申请号：US15856034
申请日：2017-12-27
申请人： Novatek Microelectronics Corp.
发明人： Tsen-Wei Chang
IPC分类号： G06F3/041 , G06F3/044
CPC分类号： G06F3/0418 , G06F3/03547 , G06F3/038 , G06F3/041 , G06F3/0412 , G06F3/0414 , G06F3/0416 , G06F3/044 , G06F3/047 , G06F21/32 , G06F2203/04112 , H03M3/396 , H03M3/422 , H03M3/438 , H03M3/458
摘要： A signal processing circuit is provided. The signal processing circuit includes an analog-front-end circuit and a filter circuit. The analog-front-end circuit is configured to receive a sensing signal from a touch panel and perform a signal capture operation on the sensing signal to output a current signal. The filter circuit is coupled to the analog-front-end circuit. The filter circuit is configured to receive the current signal from the analog-front-end circuit and perform a signal filter operation on the current signal to output a first voltage signal. The filter circuit includes an anti-aliasing filter and a comb filter coupled in series.

10. 发明授权

US09793917B2 Method and apparatus for adjusting a bandwidth of a sigma delta converter 有权
公开(公告)号：US09793917B2
公开(公告)日：2017-10-17
申请号：US14887024
申请日：2015-10-19
申请人： MOTOROLA SOLUTIONS, INC.
发明人： Joshua E. Dorevitch
IPC分类号： H03D1/00 , H03M3/00 , H04B1/16
CPC分类号： H03M3/51 , H03M3/344 , H03M3/376 , H03M3/396 , H03M3/424 , H03M3/50 , H04B1/16
摘要： A method and apparatus for adjusting a bandwidth of a sigma delta converter by adjusting a reference voltage provided to the sigma delta converter. The apparatus includes a switched capacitor digital-to-analog converter in the feedback loop of the sigma delta modulator. The sigma delta modulator determines the bandwidth mode of the converter and adjusts the reference voltage to deliver high performance functionality. In one embodiment, a multi-bit digital signal is received by the digital-to-analog converter. The reference voltage is provided to multiple capacitive circuits of the digital-to-analog converter and the capacitive circuits are activated and deactivated based on the multi-bit digital signal. The digital-to-analog converter, thus, provides a feedback analog signal using dynamic element matching.

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